Highlights

44mythspromo
EDA

44 Myths About Chip Verification eBook (Download)

Many misconceptions have emerged about chip simulation and verification tools and techniques. Download this eBook, which collects together four of our most popular 11 Myths articles...
AMD, Chiplet Summit
Semiconductors

Multi-Die Systems @ Chiplet Summit 2024

Check out the latest chiplet and packaging technology at this year's Chiplet Summit.
309588159 © Alexei Onufriiciuc | Dreamstime.com
Embedded

Ethernet Tailored for the AI Era

The latest Ethernet PHY and controller IP from Synopsys can crank out up to 1.6 Tb/s of bandwidth.
NVIDIA and dreamstime_wrightstudio_132
Embedded

NVIDIA’s Blackwell GPU: Driving the Future of AI

The latest Blackwell GPU is the result of innovations in everything from the transistors themselves to the architecture, advanced packaging, connectivity, and memory.
86230086 © Flynt | Dreamstime.com
EDA

Packaging Chiplets for Performance and Profit

When it comes to chiplets, it’s all about packaging technology.
GTC March 2024 Keynote with NVIDIA CEO Jensen Huang
Machine Learning

Presenting the Blackwell GPU @ GTC 2024

The latest NVIDIA Blackwell GPU helps accelerate artificial-intelligence chores.
Georgia Institute of Technology
Analog

Graphene-Based Transistors Receive R&D and Mass-Media Attention

Humble carbon in graphene form is the subject of considerable research effort for non-silicon active devices.
Intel
EDA

Intel Foundry Open to the World

Intel’s foundry is no longer dedicated to just its own products, but will be available to all customers. And it plans to be the second largest foundry by 2030.
Multi-Die Systems Set the Stage for Innovation
EDA

Multi-Die Systems Set the Stage for Innovation

Abhijeet Chakraborty, Vice President of Engineering at Synopsys, in his keynote at the 2024 Chiplet Summit, said that last year was an inflection point for multi-die systems.
91824901 © Forance | Dreamstime.com
EDA

EDA Helps Cultivate the Future of Die-to-Die Connectivity

Explore Keysight’s Chiplet PHY Designer tool and the game-changing UCIe standard in chip design.