MOSFET Synchronous Rectifiers Require Attention to Gate Charge

The switching speed of a power MOSFET charge-controlled device depends on the speed with which an associated gate driver circuit can charge its input capacitance. For the last 20 years, many excellent papers have addressed MOSFET switching performance as a function of first quadrant device capacitance and gate charge_[1]. This information is useful for applications using the power MOSFET as a first quadrant switch. However, it's of little value to synchronous rectifier applications where the MOSFET channel enhancement happens during the reversal of the drain voltage — a third quadrant operation. Gate charge must be considered because during third quadrant operation, the amount of instantaneous current required to fully enhance the MOSFET channel directly influences total power conversion efficiency.

Fig. 1 illustrates a typical synchronous rectifier used in today's low voltage dc-dc converter. To reduce voltage drops across the rectifying elements and increase total converter efficiency, power MOSFETs Q1 and Q2 replace the traditional rectifier diodes.

Fig. 2 compares the voltage drop across various rectifying elements as a function of temperature for Schottky diodes and MOSFETs. This graph illustrates why it's desirable to replace passive diodes with active transistors, especially for dc-dc converters with very low output voltages and high currents. A typical silicon rectifier will have a 25°C forward drop on the order of 0.6V, declining at a rate of 1.7 mV/°C. A typical Schottky diode will have a 25°C forward drop on the order of 0.33V, declining at a rate of 1.6 mV/°C. However, the ISL9N310 Power MOSFET (at ½ rated current, 17.5A) has a conduction drop of 0.175V, decreasing at a rate of 56μV/°C. The decreasing voltage drop across the rectifying element directly relates to increased converter efficiency.

As shown in Fig. 1, synchronous rectification requires a gate drive circuit to control the MOSFET switches. Because the MOSFET switches are charge-coupled devices, this gate driver must supply a current capable of charging the MOSFET's input capacitance. The charging current and magnitude determine the charging rate of the device capacitance. These two variables control the turn-on and turn-off times of the MOSFET switch.

Second Quadrant Capacitance

To evaluate the gate drive requirements during synchronous rectification, you must study first and second quadrant capacitance. MOSFET capacitances change as a function of drain voltage, V_DS. Most manufacturers' data sheets graph these functions. For example, the typical data sheet in Fig. 3 plots input capacitance, C_iss, Miller capacitance, C_rss, and output capacitance, C_oss, as a function of forward drain voltage for quadrants one and two. As shown in Fig. 3, C_oss rises toward infinity. This occurs because the negative drain voltage causes the MOSFET body diode to be forward biased where it ceases to be a capacitor. The channel also sits at infinite resistance during capacitance measurements causing a second problem in using Fig. 3 for evaluating synchronous rectification gate charge requirements. Therefore, the traditional capacitances, C_iss, C_rss, and C_oss, are of little value when trying to calculate third quadrant gate drive requirements.

Enhancing the channel during negative drain voltage creates an effective input capacitance C_{input(3rd-Quad)} value, as shown in Fig. 4, on page 31. We derived Fig. 4 by enhancing the channel and calculating a running average of instantaneous gate charge while the drain was reversed biased and the drain current, I_D, was sourced at full maximum data sheet rating, e.g. I_D=35A. You can see that the C_{sub input(3rd-Quad)} value bares no resemblance to the traditional MOSFET capacitance values, shown in Fig. 3.

To plot Fig. 4, use:

Where:

Q_G(3rd-Quad)=Instantaneous gate charge with third quadrant drain current;

V_GS=Instantaneous gate voltage (positive voltage for an N-Channel MOSFET.)

Third Quadrant Gate Charge

Fig. 5, above, plots third quadrant gate charge, Q_G(3rd-Quad), for the ISL9N310 Power MOSFET using the circuit in Fig. 6, below. In practice, the MOSFET gate has a positive bias using a constant current source while the negative current source biases the drain. Here, we set the gate current to 1mA and the drain current to 35A. As shown in Fig. 5, as the input capacitance [C_{input(3rd-Quad)}] charges, the channel enhances, and the drain to source voltage, V_SD, falls until reaching channel saturation.

Although 35A represent the maximum continuous drain current in the ISL9N310 data sheet, not all applications operate at maximum drain current. Therefore, we address the specified drain current(s) on a typical data sheet. To answer this we evaluated drain currents of 5A to 35A in 5A steps and found that the gate-voltage wave-forms for each current overlaid each other perfectly. This means the effective input capacitance, C_{input(3rd-Quad)}, and gate charge, Q_G(3rd-Quad), are independent of third quadrant drain current.

Specifications of the ISL9N310AD3 gate-threshold voltage, V_GS(th), are 1V to 3V. Typical applications include using logic level control circuitry, so data sheet specifications include +5V gate-to-source, V_GS, performance. However, a +5V gate-to-source does not fully enhance the channel (Fig. 7, above). Therefore, you don't achieve optimum performance using logic level drive signals. The Table lists data points extracted from Fig. 7, showing that a +10V gate voltage will enhance the MOSFET channel to 96% using +15V as the 100% benchmark.

Because the effective input capacitance, C_{input(3rd-Quad)}, cannot be represented by the C_iss, C_rss, or C_oss MOSFET capacitances; these traditional data sheet capacitances are of little use in predicting gate charge requirements when using the power MOSFET as a synchronous rectifier. Therefore, data sheets tailored for the dc-dc converter/synchronous rectifier applications need additional information, such as that supplied in Fig. 7.