Managing Currents in Dual- Synchronous Controllers
When a dual-synchronous controller has no load, negative inductor currents may develop. If these currents are not properly managed, they can flow backward into the power sources with undesirable results. This condition causes overvoltages and, in some cases, causes the power sources to turn off. In particular, on startup, there may be a significant period of time during which there is no load or a very-low-current load. It's important that the controller system is designed to minimize and tolerate the effects of the negative currents encountered at startup. To understand this situation, it's easier to picture the two typical controllers and their power train (Fig. 1).
The 1.5-V output of this dual controller is shown in the middle of Fig. 1, and the power trains are drawn to show that they form an H bridge. In normal operation of a dual controller, the opposite FETs (those located diagonal to one another) turn on during each phase of a clock cycle. For simplicity, the circuit of Fig. 1 has a common 5-V FET supply, no external load and equal-value inductors.
Fig. 2 shows measurements of the circuit's two switch nodes and the currents that flow in L1 and L2 during zero-load conditions. The master controller and slave controller of the circuit in Fig. 1 are alternately referred to as Channels 1 and 2, respectively. These channel designations for the circuit also correspond to the oscilloscope channel labels (CH1 and CH2) for the switch-node waveforms pictured in Fig. 2.
Fig. 2 indicates that the clock frequency is about 150 kHz, corresponding to a period of 6.66 µs. As expected, the controller's pulse widths reflect the ratios of input to output voltage. That is
PW/(period) = VOUT/VIN
or
PW = (1.5/5) × 6.66 µS
PW = 2 µS
Where PW is the pulse width of the switching waveform, VOUT is the output voltage measured in Fig. 1 and VIN is the input voltage measured in Fig. 1.
In Fig. 1, the input voltage to both of the controller channels is the same. However, if the common connection between Q2 and Q3 was broken, then different values of VIN could be applied to the two controller channels. If these input voltages are different, the two controller channels simply adjust their respective pulse widths for the common period so that their respective output-to-input voltage ratio is satisfied. This is shown in Fig. 3 for the case where the Channel 1 input voltage is dropped to 3.3 V, while the Channel 2 input voltage remains at 5 V.
An inherent problem exists with this and other PWM controllers: With no load, the current in L1 that builds up during the on-time of Channel 1 has a path backward through L2 to ground. Furthermore, during the off-time, the regulated output voltage on Channel 1 has a path to ground. This is illustrated in the schematic where Q2 and Q4 provide a path for current through L1 and L2 during one half of a cycle and Q2 and Q1 provide a similar path during the other half of a clock cycle.
In other words, during the time the Channel 1 controller should be setting an appropriate PWM pulse width, Q4 acts as a load and sinks wasted current. This current is VOUT/L2 times the time until Q4 turns off. The rate of this current parasitic in the above example is 1.5 V/1.5 µH or 1 A/µs. Similarly, when the Channel 2 controller is setting a duty cycle appropriate to the output voltage, Q1 is on and creates a parasitic load of 1 A/µs.
Note that these parasitic currents are going in the wrong direction and subtract from any desired current going into the load. Obviously, this is bad for low-current efficiency.
Another undesirable aspect of this circuit arrangement occurs when the bottom FET is turned off at the beginning of a phase cycle. At this time, the inductor current flows backward through the top FET and back into the system's power supply. This can lead to overvoltages and system failure. From a dc point of view, it only takes 50 mA of negative current to trip the output overvoltage protection on the 12-V output of an ATX supply. For a 5-V output, it takes just 100 mA to trip the supply's output overvoltage protection. While it's undesirable to have these currents in the first place, make sure any dc-equivalent reverse currents are small, relative to these numbers.
The quantitative effect of these currents can clearly be seen in the scope picture of Fig. 2. The Channel 2 negative current discharges backward through Channel 2's top FET from the time the Channel 2 bottom FET is turned off until the current discharges to zero. Fig. 2 shows this current reaching zero in 1 µS from a peak current of -2.72 A. This corresponds to an average current of 1.36 A that exists for 1 µs of the 6.66-µs cycle time. Thus, the average current over a cycle is 1.36/6.66 or -206 mA.
During this same period, there is a positive current from the supply of a slightly lower peak current of 2.16 A with a 1.08-A average for 1 µs and an average over the cycle of 1.08/6.66 or 164 mA. The algebraic sum of these two currents, -42 mA, is the net average current flowing back into the 5-V supply. DC bench measurements confirmed this number with a measurement of -47 mA. Because the ATX supply can stand -100 mA, this undesirable current does not trip off the supply.
Table 1 shows the average currents flowing in L1 and L2 as the load is increased from zero. At zero load, the two currents, as expected, are equal and opposite in direction. As the load current increases, the Channel 2 (slave controller) negative currents drop until the load current reaches about 800 mA and the negative current in L2 goes to zero. From then on, with further increase in load, the Channel 2 current is positive.
Therefore, an application with a minimum load of 800 mA will have zero reverse-current and will start with all the current being supplied from the Channel 1 controller.
When the Channel 1 controller's input voltage is reduced to 3.3 V, the Channel 1 pulse width at zero load increases to about 3.25 µs. This change reflects the lower output-to-input voltage ratio. The positive rate of rise of the inductor current during this period is (3.3-1.50)/1.5 = 1.2 A/µs. This corresponds to the lower voltage across the inductor L1. Since the output voltage is still 1.5 V and since the Channel 2 controller is still at 5 V, the L2 inductor current and pulse width stay the same (Fig. 3).
In this case, the longer on-time of Channel 1 allows for a greater buildup of negative current in L2. This current flows backward into the Channel 2 supply and is partially offset by the positive current flowing from Channel 2 during its 2-µs on-time. It's easier to see the currents that result by redrawing the scope picture, as shown in Fig. 4. This figure is drawn with the current slopes at their theoretically correct value and a peak L1 current of 2.2 A.
Here the positive current slope from the primary channel is set by (3.3 V - 1.5 V) / 1.48 µH = 1.22 A/µs, and the negative slope is set by 1.5 V/1.48 µH = 1.01 A/µs. During the 3-µs on-time, the Channel 1 current reaches zero current in 1.2 µs and reaches 2.2 A during the remainder of its 3-µs on-time. From that point, the L1 inductor current decreases until the beginning of the next clock cycle. The net positive current in the Channel 1 inductor L1 is simply the algebraic sum of the average positive and negative currents over one cycle.
That is:
I average L1 = I average positive current — I average negative current
or
I average L1 = [(2.2/2 A) × (4.0/6.66)] — [(1.22/2 A) × (2.66/6.66)] = 0.418 A.
This result agrees with the 410 mA measured L1 current in Table 2.
The net current flowing backward into the Channel 2 supply consists of the average positive current in L1 flowing backward into the Channel 2 supply, minus the average current generated during Channel 2 on-time.
This latter current is given by: I L2 = [((5.0 - 1.5)/1.48) × (2/6.66) × ½] = 2.36 A/µs x duty cycle × ½ = 355 mA.
The total current flowing in the second controller's power supply is then the sum of the reverse current plus this positive current:
I supply = -418 mA + 355 mA = -63 mA
The measured value for this current was -80 mA.
Table 2 shows the same set of currents as Table 1, except that the input voltage to the Channel 1 controller has been set at 3.3 V. This increases the zero current from 352 mA to 410 mA. The increase in zero-load inductor current reflects the increase in the pulse width of the Channel 1 controller's zero-current pulse width from 2.14 µs to 3 µs. Thus, the Channel 1 inductor current required to reduce the Channel 2 inductor current to zero increases from 810 mA to 1.2 A.
The slope of current on the Channel 1 side of the controller is 1.22 A/µs, while the slope of Channel 2 side of the controller is 2.33 A/µs. The average change in currents with load is proportional to these slopes. The ratio of these slopes and the change in currents with load is 1.91. Thus, for every ampere of current taken from the Channel 2 controller, 1.91 A is taken from the Channel 1 side.
So, to reduce the negative current in Channel 2 from 410 mA to zero, a load must draw 410 mA from the Channel 2 side of the controller. To do this, the Channel 1 side will deliver a current given by:
I Channel 1 = 1.91 × 410 mA = 783 mA
Thus, the total load that must be drawn from the controller to bring the negative current down to zero is:
I Channel 1 + I Channel 2 = 783 mA + 410 mA = 1193 mA
This agrees qualitatively with the value for L1 current of 1200 mA shown in Table 2.
This analysis provides a way to calculate the negative current that will flow in a dual controller when there is zero-load current. It also gives a way of calculating the minimum load required to avoid negative currents. This information provides the designer with the ability to design his system to stay within the negative current capability of his power sources under a worst-case condition of zero current.
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