Passive Current Sharing Boosts Power and Reliability

Passive current sharing is a method of paralleling the outputs of two or more power supplies or dc-dc converters so that they share the load near equally. This approach has strong appeal, because it is simple and inexpensive to implement, and it can be used with the latest low-cost, miniaturized power modules.

Although passive current sharing cannot be used to obtain double the current output you would get from a single converter (because one of the converters will always try to output more than half the total load current, and therefore exceed its maximum rating), it provides a highly scalable means of accommodating demands for more power, which typically result from increases in system size or functionality over time. Passive current sharing also can improve the reliability of N+1 power module configurations by reducing the stress on each converter in the system without the need for any additional active circuitry.

Unfortunately, the simplicity of this method of paralleling is not without tradeoffs — the biggest being loss of system efficiency and load regulation. Whether these tradeoffs are acceptable obviously is a design decision, and to a large degree depends upon the application. In the example presented in this article, load regulation is less of an issue because the paralleled converters are feeding an on-board intermediate bus to supply multiple point-of-load (POL) converters, which provide further down-conversion and regulation for their various silicon loads.

The advantages and disadvantages can be illustrated by paralleling two Artesyn TQW14A-48S12 intermediate bus converters (IBCs). These are wide-input 168-W dc-dc converters, primarily intended for telecom applications that convert a nominal 48-Vdc input into 12-Vdc output. TQW14A-48S12 IBCs can output up to 14 A with a typical efficiency of 95% and are not equipped with active current sharing facilities. The calculations are all based on worst-case component tolerances, for the purposes of illustration. The figure shows the two IBCs in an N+1 redundant passive current-share configuration.

In addition to the two converters, there are two Schottky ORing diodes, D1 and D2, to decouple the outputs. These are assumed to have a forward drop of 0.2 V, plus a resistive component equivalent to 7 mΩ, which models the datasheet curves for the STPS20L15 devices manufactured by STMicroelectronics.

To implement current sharing between the two converters using ORing diodes, their output voltages ideally need to be adjusted to be perfectly matched under all conditions. However, in the real world, it is nearly always impossible to achieve this degree of trim accuracy. Furthermore, in the example, for reasons of economy, the IBCs are only designed to produce loosely regulated outputs and do not offer a voltage trim facility. Consequently, there are two options.

One option is to implement an active circuit on the output of the converters to force them to current share. This approach is relatively expensive and takes up valuable board space. The second option is to employ passive current sharing, which involves putting droop resistance in series with the outputs. This droop resistance will create enough voltage drop under load to cause the two converters' voltages to equalize, and the converters will consequently current share.

To complete the circuit in the figure, we need to determine the value of the droop resistors R1 and R2. If the droop resistors are too small, then there will not be enough voltage drop under load to cause the converters to share the load. Conversely, if the droop resistors are too large, the final voltage under full load will drop too low to be useful. To determine the ideal value, we must determine the maximum variation allowed in the voltage to the load.

The first consideration is the minimum voltage the TQW14A IBCs will output under worst-case conditions. This will occur when their input voltage is at the bottom end of its permissible range (i.e., 36 V). According to the datasheet, the output voltage could then be as low as 12 V minus 10%, which is 10.8 V.

Output current to load I_out1 (A) I_out2 (A) V_out (V) Power loss due to resistance (W) Power loss due to diode drop (W) Total current share circuit power loss (W) Typical efficiency of each POL drawing half the load Total power dissipated (W) Efficiency with passive current sharing added 0 0.00 0.00 11.90 0.00 0.00 0.00 0.0% 4.32 0.0% 2 2.00 0.00 11.84 0.08 0.43 0.51 85.0% 4.78 83.22% 4 4.00 0.00 11.79 0.32 0.91 1.23 91.0% 6.01 88.69% 6 5.63 0.37 11.75 0.63 1.42 2.05 93.0% 7.51 90.37% 8 6.64 1.36 11.72 0.91 1.92 2.83 94.0% 9.00 91.24% 10 7.65 2.35 11.69 1.27 2.45 3.72 95.0% 10.07 92.07% 12 8.66 3.34 11.67 1.71 3.00 4.71 95.0% 12.33 91.91% 14 9.66 4.34 11.64 2.23 3.59 5.81 95.0% 14.70 91.73% 16 10.67 5.33 11.61 2.83 4.20 7.02 95.0% 17.17 91.54% 18 11.68 6.32 11.59 3.51 4.83 8.34 95.0% 19.76 91.35% 20 12.69 7.31 11.56 4.27 5.50 9.77 95.0% 22.45 91.15% 22 13.69 8.31 11.53 5.11 6.20 11.30 95.0% 25.25 90.95% 24 14.70 9.30 11.50 6.03 6.92 12.94 94.5% 29.77 90.27% 26 15.71 10.29 11.48 7.03 7.67 14.69 94.5% 32.92 90.07% 28 16.71 11.29 11.45 8.10 8.45 16.55 94.5% 36.17 89.86% Worst-case current sharing scenario for two TQW14A IBCs fitted with 0.02-Ω droop resistors.

The second consideration is the minimum voltage that the load can tolerate. The TQW14A IBC primarily is designed to drive POL converters, so we'll assume these constitute the load in this case. The nominally 12-V input POL converters that Artesyn produces fall into three groups, with input ranges of 10.8 V to 13.2 V, 10.2 V to 13.2 V, and 10 V to 14 V. Obviously, we cannot drive the POL converters with a 10.8-V to 13.2-V input range because there is no margin. So, for the purposes of example, we'll use the second group and limit the droop to 600 mV.

To determine the value of R1 and R2, we first need to subtract the voltage drop caused by the isolating diodes from the 600 mV, as shown below:

600 mV - 200 mV - ((14 A × 0.007 Ω) × 1000) = 302 mV

Applying Ohms law:

R1 = R2 = 0.302 V/14 A = 0.0215 Ω or 21.5 mΩ.

For the circuit, we will choose the next lowest standard value, which is 0.020 Ω. Assuming 1% tolerance resistors, the minimum value will be 0.0198 Ω and the maximum will be 0.0202 Ω.

The circuit is now designed. The question is: How well does it work, and what is the theoretical loss of efficiency? We also need to bear in mind that the resistance of the PCB conductor traces will affect the results. Because this resistance varies from application to application, we will assume a value of 0 Ω for the purposes of this example. The resistance of the PCB traces will tend to improve current sharing while decreasing system efficiency.

Through circuit analysis, the output voltage = V_out1 - I_out1 × R1 = V_out2 - I_out2 × R2, and the load current = I_outload = I_out1 and I_out2.

The individual output currents I_out1 and I_out2 can be calculated by the following formulae:

I_out1 = (V_out1-V_out2+ (R2 × I_outload))/(R1+R2)

I_out2 = I_outload - I_out1

V_out = V_out1- (I_out1 × R1)

The table shows I_out1 and I_out2 under various load current conditions.

Note that the formulae for I_out1 and I_out2 indicate a negative current for I_out2 for load currents of 5 A or less. Because of the ORing diodes, negative currents are blocked, which results in 0 A for I_out2. At the other end of the current output scale, note that passive current sharing can only be used up to 22 A — beyond this the maximum output capability of one of the IBCs is exceeded, as shown in red.

In addition, the table shows the power loss due to the resistors and the ORing diodes, together with the overall effect on efficiency. As can be seen from the table, passive current sharing is far from perfect. With the circuit constraints conveyed by the load and 1% standard parts, the worst-case load sharing is theoretically 24.4% (based on the 0.02-Ω droop resistors) with a 22-A load shared between the two converters. However, this load sharing is achieved with an efficiency loss of only 4.05%.

It is important to note that we are using worst-case figures to illustrate passive current sharing. Based on actual process capability index (Cpk) sample measured data, using extreme values, the worst-case output voltage values for the TQW14A IBC are 12.098 V maximum and 11.957 V minimum. After allowing for the voltage drop of the ORing diode, these reduce to 11.898 V and 11.757 V, respectively.

A more reasonable scenario would be to use the actual Cpk sample measured data, but with values equivalent to the standard deviation from the average. This would produce converter output voltages of 12.076 V maximum and 12.006 V minimum, giving post ORing diode values of 11.876 V and 11.806 V, respectively. Although overall efficiencies remain largely unchanged, the effect of using the more reasonable output voltage figures is an improvement in current sharing accuracy to 11%, and the paralleled IBCs will now deliver up to 25 A before the output rating of a converter is exceeded.

Passive current sharing offers an inexpensive means of accommodating increased on-board power demands without major redesign, provided the slight loss in conversion efficiency can be tolerated. Although we have chosen to illustrate the technique using two IBCs feeding POL converters via an intermediate bus, the approach also is suitable for use with conventional brick-type converters with tightly regulated outputs.

Eliminating the ORing diodes obviously would increase overall efficiency, but it would be necessary to guarantee a fairly high minimum load at all times. However, this approach is not without risk, because the FETs used by the converters' synchronous rectification stages can sink or source current when active, and power could consequently circulate between the two converters.

Other reasons for adopting passive current sharing are to increase reliability of N+1 power module configurations, and to secure better performance on boards that do not use an intermediate voltage bus and point-of-load converters. If the board contains widely distributed loads, better voltage regulation will be achieved by placing the converters as closely as possible to the loads — perhaps using both sides of the board — and the amount of copper can be reduced because the board traces will be carrying less current.