Inductor Current-sensing Boosts Regulator Efficiency

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As the demand increases for higher-current, low-voltage multiphase synchronous buck converters, a method for sensing current without the penalty of reduced efficiency is needed. To achieve the desired efficiency in their converters, designers of voltage regulator modules (VRMs) use different approaches, such as low-side FET R_DS(ON) sensing, high-side FET R_DS(ON) sensing, ground-referenced resistive sensing and inductor sensing.

But, simply selecting a particular current-sensing technique is not sufficient. To truly optimize VRM efficiency, power supply and magnetics designers need to understand each other's design goals, and both need to retune their way of designing. This article provides an overview of lossless inductor current-sensing and the affect of the inductor design. It will also demonstrate how collaboration with the magnetics designer at the beginning stages of VRM design can increase the efficiency of the finished VRM.

Basic Current-sensing

In the majority of conventional VRMs, direct resistive sensing current is accomplished by monitoring the voltage drop (current-sense information) across the R_SENSE resistor when the output current, I_O, is going through it (Fig. 1). The problem with this approach is the power loss caused by the entire output current going through the resistor R_SENSE (I_O² × R_SENSE). To minimize this power loss, lower peak voltage, usually about 100 mV, is required in the sensing resistor. Ideally, the largest voltage sensor with the lowest loss is the best way to achieve noise immunity.

VRM designers feel that losing even a small percentage of efficiency during sensing is not acceptable, so the need to find a better approach to gain back the lost efficiency is apparent. As a result, lossless sensing is becoming more popular among VRM designers.

This lossless inductor approach is easy to implement and very inexpensive to incorporate. It has fairly good accuracy and boosts efficiency. By removing R_SENSE, as in Fig.1, we can increase our VRM's efficiency, but we still need the same current-sense information, which presently comes from across C1 (Fig. 2).

Let's examine this in more detail. The voltage across the output inductor L_O consists of two parts: the voltage caused by I_O going through its dc resistance (R_dc) and I_O going through its impedance X_L. The R1 and C1 also create an ac voltage divider when placed across L_O (Fig. 3).

Writing the loop voltage equations gives:

Substituting Eq. 2 into Eq. 1 and solving for V_c:

by changing to S domain:

and solving for V_C:

Now, if {1+(S·L_O)}/R_dc=1+(R1·C1·S), then (S·L_O)/R_dc=R1·C1·S. So, if we make L_O/R_dc=R1·C1, then V_C=L_O·R_dc, which is the same information in Fig. 1.

The above derivation shows that the voltage V_c across the capacitor C1 is proportional to the voltage drop of the dc resistance of the inductor. Therefore, V_C presents the same information as inductor current. Once the L_O is calculated based on the needed energy and the R_dc is known, both R1 and C1 can be chosen accordingly, in order to match the time constant R1C1 to the ratio of L_O/R_dc.

There are several variables that will affect the accuracy of this method of current-sensing. In the equation R1·C1=L_O/R_dc, the term R1·C1 is the key value, but it cannot be determined until the other variables are defined. The following summary describes these variables.

Key Inductor Variables

Output inductor ± tolerances

Usually the inductors will have tolerances caused by the variations in core size, permeability of core material, gap size tolerances and the thermal characteristic of the core material. When separate inductors are used, the variability integral to each inductor can cause a mismatch in load sharing. That mismatch can cause one inductor to overheat and to reach saturation sooner than the others. Saturation then causes an accelerated drop in inductance and a rise in inductor current that might blow the fuse or destroy the FET.

Integrating two or more inductors into a single core structure gives a tighter inductance than two or more individual inductors in different cores. The current is shared and the inductor operates as a single unit. This creates tighter tolerances and also reduces the space required for individual inductors. Two and four inductors formed into a single structure are shown in Fig. 4.

The tighter the inductance tolerance, the better the pole location, so the loop compensation is easier to design. Keep in mind that to bring the switching ripple frequency at the pulse-width-modulation (PWM) comparator down, the ac gain of the error amp needs to be tailored, so that it doesn't degrade the VRM's transient response under a dynamic loading. It is critical that VRM designers know the tolerances of each of the magnetic parts they're using (Fig. 5).

Magnetic supplier's inductance variation

The curves of Fig. 5 show the variation of two different suppliers' inductors that meet the inductor specification. Remember, the R1C1 pair is tuned for L_O/R_dc. Which inductor should the designer use to tune his circuit?

In applications where two or more windings get connected in parallel to increase the current capability of the device, attention should be given to proper layout and connection for more accurate load sharing. Improper layout or connection will cause a winding to carry more current than it's rated for. This might cause a MOSFET's failure if the current is not limited.

Winding variations in toroidal applications

When using toroidal designs, attention should be given to the winding consistency from lot to lot. For example, the winding on the right in Fig. 6 has about 15% more inductance than the one on the left, which has a uniform winding distribution throughout the core cross-sectional area.

The variation in windings can easily result in a difference in inductance between the measured and calculated values. The RC needs to be tuned to the calculated number; otherwise, this discrepancy might create an error in current-sensing.

Change in dc resistance of the inductor

The dc resistance of the toroidal, bead or any other shaped core design will have a tolerance with respect to the tolerances in the cross-sectional area of the core used. The dc resistance has a 0.385%/°C rate of change with temperature. Usually, the current-sense amplifier's gain has a built-in negative temperature coefficient to counteract the increase in dc resistance with temperature. Without factoring in a coefficient to reflect temperature variations, the calculated resistance will be inaccurate.

Mismatched load sharing between phases

If the voltage across each inductor's phase (V-µs) plus the inductor's value could be kept the same, this would increase the chance of load sharing between each phase. In real-world applications where the MOSFETs could have a 20% difference in R_DS(ON) alone, these variations in the FET's R_DS(ON) and R_dc of the inductors could easily cause a lower voltage to appear across inductors in different phases. In effect, this will cause a higher ac ripple current for some of the phases, which might influence the saturation characteristic of the inductor that carries the highest amount of current. Generally, the larger the load, the worse the load share. The equation below shows the difference in ripple current caused by the R_DS(ON) variation in MOSFETs, the R_dc of the inductors and the inductance values in different phases:

where ΔI1=Ripple current in inductor L_O in phase one.

Tolerances of R1, C1 and improper PCB layout

Attention should be given to proper layout for a more accurate load sharing and current limit trip-point. Improper layout might cause additional voltage drop due to inductances associated with the pc board traces, which effectively changes the current limit trip point seen by the current-sense comparator. Choosing lower tolerance thick-film resistors (less than 1%) and capacitors with a good thermal characteristic — like COG types — could help reduce tolerances involved in the tuned R1C1 time constant, resulting in better current-sensing.

The input offset voltage of an operational amplifier (V_OFFSET)

Having the lowest dc resistance for an output inductor is desirable to achieve the highest efficiency in any VRM. Because of the input offset voltage of the operational amplifiers in the controller IC, the dc resistance has to be increased, so the percentage of error caused by the offset voltage is reduced. This of course will have a side effect of lower overall efficiency caused by increasing the dc resistance of the output inductor.

Proper understanding of the output inductor and its inductance variation caused by the variables mentioned above, with an understanding of the operation of the multiphase VRM and the compensation theory, allows the designer to accurately design the matching R1C1 time constant to the L_O/R_dc. Understanding real-world variables that cause a tolerance change in both inductance value and dc resistance change allows designers to incorporate all these variations into their calculations, and enables them to have more accurate current-sensing designs and fast stable loop-responses. Designers of magnetic elements must also be able to understand the affect of their magnetic designs on the current-sensing, loop, emission and other effects within VRMs and design, accordingly.

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