Shrinking geometries, one of the Holy Grails of semiconductor design, provide so many application advantages that it is totally understandable that the small is great syndrome should continue unabated. One fly in the technology ointment though is the phenomenon of soft errors. Soft errors have been around a long time and whereas certain technologies have helped alleviate the problem the fact is that shrinking geometries are creating circuit densities that are making components increasingly susceptible to the soft error invasion.
Soft errors are caused in circuits by the invasion of neutron particles that zap through a device and temporarily alter the charge that is stored in that device. Generally speaking this does not cause any long-term damage to the device, although occasionally it will, the major problem is that it creates a situation where a chip temporarily holds erroneous data.
As I said, soft errors have been around since transistors were invented and the neutron particles are generated from cosmic rays from residual radioactive atoms such as radium and thorium. It is this background radiation consisting of neurons and alpha particles that has the ability to pass through semiconductor material. But it’s not only these particular “space invaders” that can cause soft errors. Neutron invasion can originate from the chip itself. Material degradation in the device packaging and the existence of microscopic traces of radioactive materials like uranium and thorium within the material used to produce the chip and its packaging can also lead to soft errors
These disruptive elements have long been known to the military primarily because of the high altitudes that electronics have to work at in certain military applications. So a long held assumption was that neutron soft error phenomena could only happen at high altitude. Not so. These circuit invaders can get to street level although some streets are more vulnerable depending on their altitude above sea level. But what about the preventative strategies I mentioned earlier?
To some extent these have helped. Some time ago ST Microelectronics added capacitors into its SRAM memory cell. The strategy here was to increase the amount of invasive charge needed to flip a memory cell.
Today many memory manufacturers of DRAMs use embedded trench-type and stacked capacitors to enhance capacitance and there is no doubt that the use of silicon nitride helps to boost protection against soft errors.
Error correction codes have proved valuable protection against soft errors as well but these are running into trouble as process geometries shrink.
At the heart of the problem is logic density which will get denser as 28nm and 22nm processes come online. Single bit errors could be dealt with but shrinking geometries mean an increasing incidence of multi-bit errors and this where the error correcting codes become frazzled.
So we know that a neutron particle can deposit a small charge within a device and the charges within a device to hold an instruction such as zero or 1 are very small; about 1.2volts. The problem is that as geometries shrink the invasive charge required to flip those zero and 1 charges is reduced to around 0.9volts and that’s when the erroneous data is created
Such is the problem that some electronics companies are veering away from SRAM technology that is vulnerable to neutron attack because of the way it stores charges and moving more towards Flash. ASICS are also far less threatened because everything is hard –wired.
But of course all things are relative and to some extent the nuisance caused by neutron radiation inflicted data errors matter far more in some apps than others. Systems involved in computer visuals are less critical than for example medical or automotive applications such as brake and steer by wire systems. The communications industry is also very concerned about soft error disruption to services as the direction of packets could be interfered with.
So as the geometries shrink more time and money will have to be invested combating the problem and as yet no one is sure what that cost will be as semiconductor technology progress from one node to the next ground-breaking node. One thing is for sure and that is the costs need to be kept down because lets face it a lot of chip companies out there are currently under ever-increasing pressures to cut operating costs because of reduced profit margins.
Sadly this can also mean that R & D investment comes under the scrutiny of the money-men and, for the sake of maintaining technological advancement and the long term profits it can generate, nobody wants too much of that happening.