A CMOS 28nm fully depleted silicon-on-insulator (FD-SOI) process devised by STMicroelectronics (using silicon substrates from Soitec) is now available for prototyping to universities, research labs, and design companies through France’s Circuits Multi-Projet (CMP) silicon brokerage services. ST has begun releasing this process technology to third parties as it nears completion of its first commercial wafers.
Planar FD-SOI technology relies on an ultra-thin layer of silicon over a buried oxide (BOx). Ultra-thin-body transistors are built into this top silicon layer, and they offer several very attractive operating characteristics. Two types of buried oxide can be used: standard 145nm thickness, or 10nm or 25nm ultra-thin (UTBOx).
From a physical perspective, the very thin silicon layer enables the silicon positioned under the transistor body to be fully depleted of charges. The overall result is the gate can precisely control the full volume of the transistor body. This results in better performance than a bulk CMOS transistor, especially when supply voltage is reduced. In addition, FD-SOI does not require doping in the channel.
Other key advantages of this technology include the fact that it solves scaling, leakage, and variability issues to further shrink CMOS technology beyond 28nm. It provides very good electrostatic control of the transistor, and will boost overall performance as well as lower power consumption.
FD-SOI cuts the random dopant fluctuation, thereby reducing transistor threshold variability. This enables stable, dense, and high-yielding SRAM function at very low power levels.
On top of that, FD-SOI will help maintain Moore’s Law by making it easier to fit semiconductor devices into smaller pitches, which in turn increases logic density that helps keep the Law rolling forward.
The availability of this process builds on the successful collaboration that has allowed universities and design firms to access previous CMOS generations, including 45nm, 65nm, 90nm and 130nm (the latter being introduced back in 2003). CMP’s clients also have access to 65nm and 130nm silicon-on-insulator (SOI), as well as 130nm SiGe processes from ST.
A total of 170 universities and other companies have received the design rules and design kits for ST’s 90nm CMOS process. And more than 200 universities and companies have received the design rules and design kits for the ST’s 65nm bulk and SOI CMOS processes.
Now ST’s 28nm CMOS bulk technology is being offered by CMP, and so far approximately 60 universities and microelectronics companies have received the design rules and design kits. In fact, 16 integrated circuits have already been manufactured.
The CMP multi-project wafer service allows organisations to obtain small quantities of advanced ICs. The cost of the 28nm FD-SOI CMOS process has been fixed to 18,000€/mm 2, with a minimum of 1mm 2.