Implantable medical devices present a challenging set of design problems. They must be small, lightweight and survive an environment–the human body–that is constantly trying to destroy them. They must also have an extended operational life on a nonreplaceable battery.
Cardiac Pacemakers Inc. (CPI) manufactures medical devices such as pacemakers and implantable defibrillators, so the quality of our products simply cannot be compromised. Today, CPI offers a product that controls both chambers of the heart and lasts more than five years on a battery one-fourth the size of devices developed in the 1970s. The contradicting requirements of smaller size and increased functionality squeeze out test points in the face of an increasing need for testability and reliability.
In recent years, a new method of testing ASICs–IDDQ testing–has risen. IDDQ stands for the quiescent state Q of the power supply current IDD. IDDQ testing is becoming vital to the manufacture of medical devices since it increases test coverage and helps to assure the high quality demanded by this market.
Figure 1 shows how IDDQ testing fits into the overall test strategy. The faults detected by the three basic testing methodologies are represented as circles mapped onto the field of all possible faults.
From this diagram, you can see that many of the faults detected by stuck-at fault (SAF) testing are also detected by functional or IDDQ testing. This redundancy in test coverage is desirable since the products being tested are life-sustaining devices.
Pacemakers use custom CMOS ASICs to keep their power low. They incorporate both digital and mixed-signal designs. Space is at a premium and everything that can be done to save power is used, including gating of clock signals. This can reduce power, but at the same time makes testability difficult.
CPI is always looking for a solution to the problem of increasing test coverage while reducing the number of test points and keeping test times low. Currently, we are using advanced ATE, high-end workstations and software to generate test vectors, digital signal processing for mixed-signal devices, and industry-standard testing techniques to achieve the highest possible quality in our devices.
IDDQ is a natural extension of the search for high quality, since it can observe every circuit node without adding any test points. It can also detect the mode that the CMOS circuits are most likely to fail.
IDDQ detects the types of failures inherent in the CMOS ASICs used at CPI. These circuits don’t usually fail high or low; rather, they will most likely fail with their outputs at a midpoint between the battery supply and ground. This state is difficult or impossible to detect with SAF testing.
The failure mechanisms that cause these faults include bridging defects, such as gate oxide shorts, polysilicon or metal bridges between the circuit nodes, soft pn junctions and transistor punch-through. Open circuit defects–for example, missing metal, improper etching, electromigration, pattering errors, and opens in diffusions or polysilicon due to mask or fabrication errors–are also caused by these mechanisms.1
IDDQ testing can detect more faults than SAF or functional test methods alone because it has higher observability and more accurately models the failure mechanisms of CMOS ICs. IDDQ detects faults that draw more current; that is, failures that tend to turn transistors or gates on. It cannot detect failures that tend to turn transistors off since these faults result in low current draw, which is the same as the passing state of a good circuit.
Test Setup
Test coverage is a function of where the IDDQ test limit is set. In general, the lower this limit, the better the coverage. However, we have found it is possible to set the limit so low that no parts will pass. The range of currents is quite large and can go as low as 50 nA.
It is also possible that the current draw of some vector states in the ASIC will plateau at a higher level than the limit for the IDDQ test for the rest of the IC. These states must be identified and masked out of the test to avoid failing an otherwise good chip.
The main trade-off is test times. To measure currents in the nanoampere range requires the use of parametric measurement units, which take an absolute measurement of the current. The tester software compares this value to the test limit. While this technique is very accurate, it can take too long for production testing of ASICs.
Testing Methodology
To speed up these test times, have some analog circuitry do the comparison against a voltage reference. This technique allows precise measurements to be made without requiring any software overhead. The circuit is much faster but limited by the signal-to-noise ratio of the test fixture, the DUT and the tester itself. It is also limited by the lot-to-lot capacitance variation of the ASICs. This variation can be as much as 15%, which adds uncertainty to the IDDQ test measurement.
Each test vector is chosen to excite, or toggle, as many nodes as possible. This drastically reduces the number of test vectors needed to get high coverage, since it is only required that a node be switched from one state to another to test it.
Every circuit node is observable through its power supply connection. And herein lies the inherent power of IDDQ–almost infinite observability. Every node must be connected to the power supply to operate and the power supply is always an observable pin.
Each IDDQ test vector, however, excites a different number of circuit nodes. The paths that connect these nodes have capacitance and this capacitance varies as much as 25% from vector step to vector step.
When this variance is added to the 15% lot-to-lot differences, a 40% change in circuit capacitance can be observed on known-good circuits. This makes it difficult to set an absolute test limit for the IDDQ current.
This affect is observable as a variance of the time it takes the IDDQ current to discharge the combined capacitance of the DUT and the test fixture. The more the capacitance, the longer the circuit will take to discharge.
We currently add delays to the test vectors to allow the circuit to integrate the device capacitance. The amount of delay is determined by the voltage desired at a certain current draw for a given device capacitance. Typically, 1-µs to 100-µs delay times are used for each IDDQ test vector.
The circuit is powered at the highest voltage at which it will run to test worst-case conditions. This will detect marginal failures, since the higher voltage will tend to raise the current draw above the IDDQ test limit.
The Derivative Amplifier
To meet the needs of high test coverage, short test times and high quality with decreasing room for test points, we developed a circuit that would meet all of these conflicting needs. We tried several other circuits before settling on this one, but chose it because it decreases test times without sacrificing test coverage.
The first stage of this circuit is a derivative amplifier (Figure 2). This is a classic op-amp circuit made by placing a capacitor, C3, in series with the negative input and a feedback resister, R2, from the output back to this pin. The gain of this stage is given by:
(iddq)(R2)(C3)
Viddq = ___________________
(C2 + CDUT)
The second stage is a gain block set to 100. The output of the derivative amp is low so the second stage is needed to boost the output to a range where the tester can read it. It is desirable to measure IDDQ currents in the 200-nA range for characterizing the DUTs during failure analysis. Adding the second gain stage accomplishes this, giving the transfer function of the entire circuit to be:
(iddq)(R2)(C3)(100)
Viddq = ____________________
(C2 + CDUT)
Speed is not the only advantage of this circuit. While the derivative of a ramp is a level whose value is a direct function of the slope of the ramp, the derivative of a transient is a shorter transient called an impulse function.
A transient happens to the charge injected through the analog switches when they are opened to begin the IDDQ measurement. The circuit takes the derivative of the charge injected by the analog switches (a short pulse) and turns it into an even shorter pulse, nullifying its effect.
A critical value is capacitor C6, which is placed in the feedback loop of the derivative amp. Its value ranges from 20 PF to 40 PF. Any less will cause the circuit to ring and can actually slow it down. Any more capacitance and the rise time increases. This also will delay the time before the IDDQ measurement strobe can be sent. The strobe timing can vary over a range of 5 µs to 100 µs. The only penalty is the possibility of droop on the output voltage (Figure 3).
The analog switch is opened to start the IDDQ measurement. At this time, the DUT is powered only by its own capacitance and any capacitance on the test fixture. As this current decays, the voltage on the capacitor also decreases.
The actual measurement of the IDDQ current is made inside the tester. An internal tester resource compares the voltage of the op-amp against a fixed threshold. If the DUT is good, the voltage will be below this level. If it is faulty, the voltage will be above the trip point and the part will fail that vector step.
The Integrated Measurement Systems XL60 Test Station enables us to program the VOH level to be the test limit. If the IDDQ current is above the value programmed for VOH, the tester will indicate a failure for the vector that was active at that time.
We chose the IMS XL60 to debug the derivative amplifier IDDQ circuit because this tester provided the necessary tools to control it. Creating the vectors to strobe the IDDQ enable line was a simple matter of programming three lines into the vector memory on the Pattern Control screen. Then we used the repeat feature to extend the time of the vector to meet the setup requirements of the IDDQ circuit.
Adjusting the IDDQ detect level and the timing of the measurement strobe was done on the Operating Conditions screen. All that was required was to type in the threshold value and the sample time.
It is important to separate power supply lines, keeping the digital power supply lines separate from the analog lines. The current draw of a good analog circuit may be higher than the IDDQ currents and can make it difficult or impossible to measure them accurately.
It is also important to separate the output pin drivers from the digital supply lines. These circuits can interfere with making accurate IDDQ measurements.
Capacitor C2 is connected in parallel with the DUT and is used to swamp out lot-to-lot variations and other capacitance differences from the test vectors. Its actual value is a function of the chip capacitance of the ASIC-under-test and is determined empirically to be five to 10 times this value. A value for C2 that gives a 1-µA current draw and an output of 200 mV from the gain stage is a good operating point.
Resister R1 and relay K1 are used by the diagnostics to check the circuit before testing parts. The diagnostic software closes the relay when the DUT is not connected. R1 is chosen to provide a 1-µA current load across C2. The software then confirms that the output of the gain stage is at 200 mV and the circuit is ready to test.
The derivative amplifier has no charge injection problems, and test times can be sped up considerably over other circuits that we have tried. This may make it possible to use all test vectors instead of a select few, depending on the number of vectors and the test times allowed. The circuit only adds small amounts of hardware to the application board and uses the tester resources to make the high-accuracy measurements.
This IDDQ circuit is based on research done by Sandia Laboratories. Our industry relies on standards to justify our test methodology. Standards being developed by the QTAG committee will eventually consolidate much of this research and should result in a small IC that could be placed as close as possible to the VDD pin of the DUT, simplifying board layout and reducing noise pickup.
IDDQ testing improves the reliability of CMOS circuits by finding faults common to CMOS IC processing. This translates directly into higher reliability for battery-operated medical life-support devices, which is a benefit to the physicians and patients who use these devices.
References
1. Hawkins, C.F. Soden, J.M., Righter, A.W., and Ferguson, F.J., “Defect Classes–An Overdue Paradigm for CMOS IC Testing,” International Test Conference, October 1994, pp. 413-425.
2. Keating, M., and Meyer, D., “A New Approach to Dynamic IDD Testing,” International Test Conference, September 1987, pp. 316-321.
3. Mallarapu, S.R., and Hoffman, A.J., “IDDQ Testing on a Custom Automotive IC,” IEEE 1994 Custom Integrated Circuits Conference, May 1994, pp. 405-408.
About the Author
Steve Ehlscheid is an Electronic Engineer for Guidant’s Cardiac Pacemakers’ business unit. He received a B.S.E.E. degree from the University of Illinois in 1975.
IDDQ testing
Semiconductor test
IC test
Medical Electronics Test
Copyright 1995 Nelson Publishing Inc.
August 1995
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