Design for Testability and the Effects on Test-Fixture Fabrication

In the last few years, designing for testability (DFT) has become more complex—but also sometimes easier to implement because of the DFT tools now available. Technologies such as surface-mount devices (SMD), in-line devices, ball grid arrays, small flexible printed circuit boards (PCBs) like PCMCIA cards and more capability on smaller real estate stretch the boundaries of test.

In satisfying these new criteria, it is important to recognize the need for a testability plan and to understand its effects on test-fixture fabrication. By understanding the positive results if design guidelines are followed, and the trade-offs when guidelines are bypassed, you can better understand the effect on time to market and total cost of test.

A test fixture is a device that connects a UUT to a test system. The most common application involves a PCB as the UUT and a bed-of-nails or vacuum-actuated test fixture. The test fixture is loaded with spring-loaded probes (nails) that contact the UUT when vacuum is actuated. These nails are then wired to the fixture interface, which directly mates to the test system. Because finished fixtures are customized to test one product, there are many considerations when building a test fixture.

Common Causes of Vacuum Leaks

In a bed-of-nails fixture, the top plate is movable. When vacuum is actuated through the vacuum port of the fixture, it not only pulls the top plate downward, but also holds the UUT onto the top plate while the nails access the nodes. As a standard, fixture-plate seals and UUT seals are built into the finished fixture to prevent vacuum from leaking.

Certain conditions can create vacuum leaks and, as a result, require special considerations:

Lack of available vacuum area in the fixture.

Open vias on the UUT.

By calculating the total bottom-plate area available for vacuum (available lb psi/in.²) and comparing this with the total amount of probe force (pressure) pushing upward on the UUT, a fixture supplier can determine if the UUT will pre-seal properly.

If the probe force is greater than atmospheric pressure, the UUT will not seat properly on the top plate and a vacuum leak will result. Fixture sizes should be selected to allow enough area for vacuum to ensure proper sealing.

With open vias in the UUT, a mechanical hold-down gate is used to seal the UUT to the fixture top plate. A mechanical hold-down gate is a hinging mechanism that opens and closes over the board, using finger-like extensions to contact the UUT. These fingers hold the UUT onto the top plate of the fixture, countering the pressure of the probes contacting the bottom side of the board.

The addition of a hold-down gate (or overclamp) usually involves isolating the probe field from vacuum. This isolation decreases the total vacuum area available for pulling the top plate down onto the probe field. Again, probe force vs vacuum area must be considered to ensure proper fixture sizing.

Alignment

One of the most basic testability criteria deals with the capability of a probe to reliably contact its target. It has been a standard in electronic board manufacturing and test that a test-pad size of 0.035″ on the UUT is required for normal probe contact. This is based on both board and fixture tolerance, including UUT datum to test pads, tooling holes, fixture drilling and probe accuracies. To ensure that the nails of the test fixture accurately contact the test points on the UUT, both fixture plates as well as the UUT must be aligned to the fixture.

All PCBs should be designed with tooling holes to accurately align the board to the fixture. The preference is a maximum of two tooling locations that are diagonally opposed in the corners of the PCB. If tooling holes are not available, the alternative is to “cage” the UUT.

Caging is a method of locating dowel pins at the perimeter of the UUT in the top plate. Although this method will secure the UUT on the fixture, it is not as reliable for providing consistent and accurate alignment of the UUT to the fixture while under test. This method is particularly unreliable on small targets and is not recommended.

Probing Techniques for Small Targets

Concerning small targets, the minimum test-pad size when using normal probing techniques is 0.035″ (DFT guidelines determined by the Surface Mount Technology Association). However, it is not unusual to see pad sizes considerably less then 0.035″.

Two methods can cope with these smaller pads:

Guided-Probe Technique

—in which a funnel-shaped hole in the diaphragm plate “guides” the probe to the target. The UUT side of the funnel hole is kept to 0.010″ larger then the probe diameter, which reduces the radial end play of the probe.

Experience shows that targets down to 0.025″ can be reliably hit with a guided probe. The drawbacks of this system are increased wear on the probes and the diaphragm plate.

There is also concern about contaminants from the UUT, such as solder flux, closing the diaphragm plate hole to a point where probe travel is impeded. Additional steps can be taken in the fixture fabrication, such as using delrin for reducing wear.

Captive-Probe Technique

—in which the probe plate actuates a second probe assembly mounted in the diaphragm plate, making direct contact with the target. This eliminates the radial end play associated with fixture probes.

With tolerance maximized, targets down to 0.018″ can be hit reliably with the captive probe. In practice, the captive-probe technique has effectively accessed targets as small as 0.015″ and 0.013″. A mix of standard probe technology and captive probes can be used on a fixture. Either of these methods will increase fixture costs, while fabrication time is transparent.

Collisions

Going hand-in-hand with test-pad size is the center-line spacing between test pads, also referred to as pitch. Manufacturers offer probe standards for 0.100″, 0.075″ and 0.050″ pitch. Using the 0.035″ test-pad size and 0.050″ center-line spacing, there will be 0.015″ of free area between test pads, which is the minimum desired. Several software packages are available that effectively evaluate board design for conditions such as pad size and collisions. “Collision runs” determine the center-line spacing between the targets on the UUT.

The minimum center-line distances for 100-, 75- and 50-mil locations vary slightly in different software packages, but the distances are usually user-defined. A typical collision setting is 80 mils or greater for 100-mil drilled holes, 66 mils or greater center-line spacing for 75-mil drilled holes, and 49 mils or greater for 50-mil drilled holes.

Once the software is “aware” of the center-line spacing, settings can specify that 100-mil test points be selected wherever possible. Maximizing on 100-mil locations reduces the cost of the fixture and wiring time, since 100-mil probes are less expensive than 50-mil probes and are wired semi-automatically at a higher point-count per hour. In addition, 100-mil probes and sockets have a thicker diameter, making them more durable in today’s manufacturing environments.

Keep-Out Areas

CAD departments will analyze customer-supplied files and information. One of the more serious problems arising in the data-processing state is inaccessible test locations. The proximity of a probe to the edge of the card or another component is critical in determining its accessibility as a test point.

Sections of a UUT that should be void of any probe locations are keep-out areas. Keep-out areas must be factored into the board design to obtain proper coverage without risking costly fixturing techniques or damage to the UUT.

In the past, a fixture seal required that a 0.100″ perimeter be void of any test nails on the bottom side of the UUT. This industry standard has changed, however, and 0.065″ is now sufficient. Any probe within this perimeter should be relocated.

As a secondary option, the mold is cut to make way for the test point, and the probe is isolated. This can degrade the quality of the board seal if there are too many points within 0.065″ of the edge of the UUT or isolation is not practical because other test points or devices are too close.

In this case, an overclamp can also be used because the board is isolated from vacuum and a seal is not required. But the addition of an overclamp increases the overall price and weight of the fixture. Typically, test points should not be located less than 0.100″ to the edge of a component, as probing these points can result in crushed probes or damaged components.

For test points close to components taller than 0.250″ on the probe side of the UUT, additional spacing considerations are determined by how much machining into the fixture plate is required. The fixture plates need to be relieved of material to properly seat the board. Clearances of 0.100″ are also recommended for devices on the bottom side of the UUT being tested via opens technology.

Opens technology is a means of testing a device for open circuits using a sensor plate in physical contact with a device. The clearance is necessary to accommodate the sensor plate of the opens probe.

Software Tools

Recent developments in software have produced packages such as FABMASTER, C-LINK and UNISOFT that offer many tools to check for incompatibilities between test requirements and the board design. The software’s flexible input structures revolve around front-end translators designed to read a multitude of CAD package outputs. Once files have been read and translated, you can activate several algorithms.

The programs identify nonprobeable conditions, such as surface-mount, and automatically adjust probe placement. The systems also minimize probe placement on top-access and close-centered test locations, and maximize the use of vias and test pads on difficult-to-access networks. This flexibility aids fixture manufacturers in keeping down the cost of fixture fabrication and build time.

The software is also invaluable for relocating test points when needed. Highly populated boards raise more sealing issues, since additional springs and stops must be used to compensate for the combined force of the concentrated probes against the UUT.

The additional sealing measures prevent UUT damage caused by variations in board flex during vacuum. This is particularly true for boards with large gate arrays and connectors where high concentrations of probes are likely.

Test points should be as evenly distributed as possible across the UUT for optimal probe access and fixture seal and for minimal UUT deflection. Promoting even distribution also helps keep fixturing costs to a minimum.

In retrospect, to facilitate board test, several conditions must be met in the design stage. We have demonstrated how even a few discrepancies in the design of a board can increase fixturing costs and production time.

Unfortunately, the design phase is becoming increasingly difficult due to spacing limitations, high-speed test requirements and new board technology. As designers address these more stringent demands, the need for close, well-informed relationships between design, test and fixturing becomes more apparent.

About the Author

Lynelle D’Aquila has been employed by TTI Testron since 1986 and is currently Director of Information Management Systems. Before joining TTI Testron in 1986, she was a computer programmer and consultant. Ms. D’Aquila holds a B.S. degree in computer information systems from Rhode Island College. TTI Testron, 41 Century Dr., Woonsocket, RI 02895, (401) 766-9100.

August 1996