Scan-based design-for-test (DFT) techniques have been in use for a long time; but until now, the process of inserting scan into a design has mainly been manual. Today, most of the research and development is focused on automatic test pattern generation (ATPG) for full and partial scan designs. And with synthesis tools coming of age, there is more interest in test synthesis and automatic testability insertion.
Basics of Scan Design
Scan design is based on the concept that if the values in all storage elements in a design can be controlled and observed, then the test-generation and fault-simulation tasks for a sequential circuit can be reduced to that of a combinational circuit. Controllability and observability are achieved by means of special storage elements with shift and parallel-load capabilities.
A control signal switches between the normal mode of operation, which uses the parallel-load capability, and a scan mode, in which the storage elements are linked in the form of a shift register known as the scan chain. The storage elements can be controlled by shifting the desired data into the scan chain and observed by shifting out the data in the scan chain. Figure 1 shows an example of a scan storage element and scan chain.
In this example, the scan-enable signal (SE) selects between the data (D) input and the scan input (SI). When SE = 0, the value at the D input is captured into the flip-flop at the rising edge of the clock (CLK), and this is the normal mode of operation.
During the scan mode (SE = 1), the value at the SI is captured into the flip-flop at the rising edge of CLK. The SI is connected to scan output (SO) of the previous flip-flop in the scan chain as shown.
Known as mux-scan or multiplex-scan, this is the most common form of scan. Other variations of the basic scan-design concept include level-sensitive scan design and random-access scan.
Design Rules for Scan
To use the scan methodology, certain design rules must be followed. In particular, scan places restrictions on the clocking schemes that may be used in the design.
For the scan chain to shift properly, all scan elements in a given scan chain must have the same scan clock. Multiple clocks may be used if they are made to appear as a single clock. Flip-flops clocked by internally generated clocks can be included in the scan chain only if their clocks can be made equivalent to the shift clock.
In the example in Figure 2, flip-flops A and C can be included in a scan chain. However, it may not be possible to include flip-flop B in the same scan chain unless its clock is multiplexed with a test clock.
It is possible to include flip-flop B in a different scan chain from flip-flop A. In this case, when the scan chain containing B is being shifted, flip-flop A must be maintained at a 1 for the CLK signal to propagate to flip-flop B. Also, to capture data into flip-flop B, it may be necessary to initialize flip-flop A to a particular value.
Another option would not scan flip-flop B. In this case, a sequential ATPG may be required to detect some of the stuck-at faults present in the circuit.
Asynchronous Set/Reset Logic
All asynchronous sets and resets must be disabled during the scan shift operation. If the sets and resets are controlled by an external pin, then this can be achieved by constraining the pin to the inactive state during the scan shift operation. If the set or reset to a flip-flop is internally generated, it may be necessary to use additional logic to control it during the scan operation.
Internal Three-State Logic
To prevent bus contention during the scan chain load and unload operations, three-state elements driving the bus must be controlled appropriately. If the enable line of a three-state element driving a bus is derived from a scan cell, it must be disabled during the shift operation.
Embedded RAMs
Most ATPGs require the state of the RAMs to be unchanged before and after a scan operation. This implies that no new data should be written to the RAM during the shift operation.
To achieve this, either the write-enable signal to the RAM must be controllable from the primary inputs or it must come from a non-scan flip-flop with the capability to hold its value during the scan operation. If this is not the case, additional logic may be needed to control the write-enable signal.
Inserting Scan Into An Existing Circuit
All of these concepts have been implemented in a software product called DFTAdvisor. DFTAdvisor accepts a gate-level netlist of the circuit along with the cell library.
Information about clocks and pin constraints, if available, can also be specified. First, a scan rules checking operation is performed on the circuit. For each flip-flop, DFTAdvisor checks whether the clock and the set/reset signals are controllable. Based on this information, each flip-flop is marked as being scannable or non-scannable. In the case of non-scannable flip-flops, an additional check is performed to see if it can be made scannable by the addition of extra test logic.
At this point, you have several options. It may be possible to make some of the non-scannable flip-flops scannable by defining additional clocks to the system or by imposing certain pin constraints. If no additional clocks or pin constraints can be identified, you must decide if it is acceptable to use test logic to make the flip-flops scannable. If it is, DFTAdvisor will insert the necessary logic and mark those flip-flops as scannable. Only flip-flops that are considered scannable by DFTAdvisor may be targeted for scan replacement.
Modifications to Clocks
To make a particular flip-flop in the circuit scannable, it may be necessary to provide a different clock to it during the test mode. This clock, referred to as the test clock, is used for scan loading and unloading as well as for data capture. DFTAdvisor accomplishes this by multiplexing the original clock with a new test_clock. An additional test_mode signal is also required to control the multiplexer.
Figure 3 shows an example of clock multiplexing. The test_mode signal is different from the scan_mode or the scan_enable signal that is only active during the scan chain load/unload operation. The test_mode signal is active for the entire duration of the test. As a result, the logic used to generate the original clock to the flip-flop will become untestable since it is not exercised during the test mode.
Handling Asynchronous Set/Reset
DFTAdvisor identifies uncontrollable set/reset signals and gates them with the test_mode signal so they can be controlled to the inactive state during testing. Once again, the test_mode signal is used rather that the scan_enable signal. This prevents the values loaded by the scan operation from being disturbed as soon as the scan_enable is turned off.
In the example in Figure 4, the reset input of flip-flop B was directly connected to the Q output of flip-flop A in the original circuit. Since the reset is active low, DFTAdvisor uses an OR gate to disable the reset in the test_mode. When the test_mode = 0, the reset is controlled by flip-flop A.
Inserting Scan Chains
Once all the decisions regarding scan and test logic insertion have been made, the tool can perform the scan replacement and scan chain insertion or stitching. DFTAdvisor can insert single or multiple scan chains. Typically, all flip-flops on the same clock are put in a single scan chain.
It is possible, however, to limit the number of flip-flops in any given scan chain. In this case, multiple scan chains will be created if the number of flip-flops exceeds this limit. DFTAdvisor can optionally merge flip-flops controlled by different clocks into the same scan chain, but skew requirements must be considered.
The order of the flip-flops in the scan chain can also be specified to the tool. This information typically comes from the placement tool.
Selecting a Scan Methodology
Several factors must be considered when selecting a particular scan methodology. Typically, the goal is to obtain the highest possible product quality while minimizing various costs involved. These costs include the area and performance impact of using scan design as well as the increase in design time required to implement scan.
Full Scan vs Partial Scan
With full scan, every single-state element in the design is replaced by its scan equivalent. You can expect close to 100% stuck-at fault coverage and the increase in design time is predictable. Also, faster combinational ATPG algorithms can be used, allowing faster test-generation times and better test-vector compression. Full scan also allows for better diagnostic capability if there is a failure. The area and performance impact of this methodology, however, is the highest.
Partial scan allows you to trade off between area and performance with fault coverage. In this methodology, only a portion of the state elements is selected for scan, and the area and performance impact may be reduced without significantly sacrificing fault coverage. It also allows you to relax scan design rules in portions of the circuit not using scan. All this is at the expense of increased design time compared to full scan.
A partial scan implementation requires more design discipline and includes a testability analysis step where scan is selected and inserted. For an optimal selection of the state elements for partial scan, the entire circuit (targeted with scan) must be available so that the testability impact of all the sequential elements can be considered. Since chip design is typically a parallel development effort, it may not be feasible to wait until all blocks are completed before selecting and inserting scan. With partial scan, the ATPG complexity is greater, and slower sequential ATPG must be used, which results in a higher test-generation cost.
In general, selecting a particular methodology involves making a set of engineering trade-offs. However, it has been demonstrated often that using some structured DFT technique such as scan, whether full or partial, is always better than not using any. In the long run, paying the additional cost up front will not only save engineering cost (for manual test-vector development) but also result in a better quality product and a faster time to market.
About the Author
Susheel Chandra is the Marketing Manager for the DFT Group at Mentor Graphics. Before joining Mentor, he was Director of Technical Services at CheckLogic Systems, and held technical staff and engineering project management positions at Sony Microsystems and Crosscheck Technology. Mr. Chandra has a Ph.D. in electrical and computer engineering from the University of Illinois, teaches DFT courses at the University of California and holds three U.S. patents. Mentor Graphics, 8005 S.W. Boeckman Rd., Wilsonville, OR 97070, (503) 685-7000.
Copyright 1996 Nelson Publishing Inc.
September 1996
|
|