The next test challenge has been identified. System-on-a-chip (SOC) devices are here and present a new set of formidable test challenges. With characteristics that affect basic test methodologies, SOCs pose a number of testing problems for the designers and manufacturers of these devices and the providers of automatic test equipment (ATE).
The most significant changes in ATE requirements are the result of stitching together, on a single piece of silicon, circuits (cores) that historically have existed only as individual devices. As a result, we are seeing the need to quickly generate and debug high-speed digital patterns obtained from several sources. Pattern sources include a variety of simulation environments, vectors supplied as part of the intellectual property (IP), automatic test program generators (ATPG), and perhaps, vectors ported from other ATE platforms.
Simplicity is the key. The more complex the programming model for timing and patterns, the more difficult it becomes to map vectors to the tester and the device under test (DUT). In general, ATE requires several types of information per channel/per device clock cycle to completely describe the waveform presented to the DUT pins. The ATE must be able to select various combinations of information during each device clock cycle, effectively changing any aspect of a waveform on the fly:
- Vector Data—Is the DUT pin level high, low, or something else?
- I/O State—Is the DUT pin currently an input or output?
- Format—What is the DUT pin doing when data is not valid?
- Period—How long is the device cycle? (A tester cycle equals one or more device cycles.)
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Timing—Where in the device cycle will data, I/O, and format events take place?
ATE Vector Requirements
The simplest model for vector generation provides a complete description of each element on every pin in every device cycle. Separating out timing and formats for the moment, a minimum of five states is required when testing digital devices. Additional formats such as Compare Midband, Compare Valid, and continually keeping a Comparator Window open are useful and can bring the total number of states to eight.
1 – Drive Data High
0 – Drive Data Low
H – Compare Data High
L – Compare Data Low
X – Driver Off/Ignore Compare
M – Expect Midband (neither high nor low)
V – Expect Valid Data (either high or low)
W – Keep Comparator Window open
To independently select one of the five to eight states, each test-system channel must provide a minimum of 3 bits of data (23 = 8). Since each DUT pin can change its required state on the fly, those bits must be available in each device cycle. Anything less and waveform compromises must be made that jeopardize the quality of the test.
Timing Architectures and Programming Models
Modern ATE, while providing the required timing and waveform flexibility at tester base data rates, generally has fallen short when base rates are exceeded. ATE data rates can be increased by constructing multiple DUT waveforms in a single tester cycle. Historically, this is accomplished either by adding to the number of data bits available per tester cycle or by channel multiplexing with the corresponding loss of available tester channels. These techniques require that test engineers and ATPG software fully comprehend the extremely complicated programming model needed to successfully create and debug the resulting timing and vectors.
As noted in Figure 1 (see June 2000 issue of EE), high-speed waveforms at two, four, or even eight times the tester base rate can be constructed using special modes. Tester Waveforms A, B, C, and D must be carefully interleaved by the programmer or ATPG tool to build the Desired Device Waveform.
Current programming models dictate that timing for each DUT cycle reference the beginning of the tester cycle. It is up to the test engineer or ATPG software to keep track of where each DUT cycle appears in the tester cycle and add the appropriate amount of time to each edge.
As an example from Figure 1, all edge timing programmed in tester cycle 1C must be increased by an amount equal to the sum of periods programmed for cycles 1A and 1B. During program debug and device characterization, the same complex analysis must be performed. Any change to periods for cycles 1A or 1B must be reflected in timing for cycle 1C. Test-program generation and debug time can be significantly impacted, compromising time to market.
DUT-Cycle Timing
A new ATE timing architecture, designed to focus on device requirements, provides the flexibility at frequencies from less than 25 kHz to 800 Mb/s. This new DUT-cycle timing programming model, illustrated in Figure 1, not only required innovative design, but also a breakthrough in semiconductor technology.
Implemented in a combination of submicron CMOS and IBM’s silicon germanium (SiGe) process and accessing pattern data at full device cycle rate, the vector and timing model of the new architecture match device operation. Backed by two independent pattern generators, both creation and debug of high-speed patterns are greatly simplified.
Running off an 800-MHz internal reference clock, the DUT-cycle timing system can provide a new device waveform every 1.25 ns. If higher speeds are needed, tester channels can be multiplexed for cycle times down to 625 ps (1.6 Gb/s). The following are available on the fly in every device cycle:
- Independent period per DUT cycle.
- Three data bits per pin for a full eight logic states including masking.
- Waveform format.
- Independent timing for all event generators, programmed relative to the beginning of the DUT cycle.
By providing all the required information in each DUT cycle, the ATE programming model is an exact match for the Desired DUT Waveform. I/O state, drive timing and format, compare timing and mask, and period can be changed on the fly.
Why CMOS and SiGe?
ATE timing systems typically are composed of a combination of digital and mixed-signal/analog circuits. The digital portion of the timing system determines the reference clock cycle in which a particular event will happen. The mixed-signal portion establishes where within that reference clock cycle the event actually occurs.
Correct design of the high-speed mixed-signal circuitry is substantially more difficult and time-consuming than the digital circuitry. Since the final timing stages must run at full speed, they usually require full custom ASICs manufactured in advanced semiconductor technology. Using a combination of advanced CMOS technology for the digital portion and SiGe for the final mixed-signal stages, all three key attributes of an ATE timing system—speed, flexibility, and accuracy—can be successfully addressed.
CMOS for Flexibility
As illustrated in Figure 2, DUT-cycle timing generators are responsible for combining input data from several sources including pattern data, timeset and format addresses, calibration correction values, and strobe results from the pin electronics comparators. Outputs include event types and associated timing values sent to the event generators. Since devices run at a variety of speeds, the test system must support frequencies from a few kilohertz to hundreds of megahertz, all at resolutions down to a few picoseconds.
Using leading-edge CMOS technology and careful design, accurate clock references can be generated at 800 MHz. By referencing the timing system to that 800-MHz clock and treating programmed timing as a combination of gross (digital) and fine (analog) values, the DUT-cycle timing system supports 10-ps resolution and values greater than 40 µs. This is the equivalent of a 23-bit counter running at 10 GHz.
The digital portion of the DUT-cycle timing system is, at its core, a collection of large fast math engines that counts clock cycles and calculates remainders. Summing DUT period values, programmed event times, and calibration correction terms, these timing generators keep track of four types of information for each tester channel:
- Events to generate and when they are to occur, based on pattern data, format, and programmed timing.
- The number of clock cycles that has occurred since the beginning of a pattern.
- The number of clock cycles required before each programmed event can be generated.
- The amount of time required after the clock for each programmed event to occur.
The Event Generator receives event-type and edge-timing data from the Timing Generator, as shown in Figure 3. That data is entered into an event queue with each event uniquely identified by type and time.
Events are placed in the queue in the order in which they will occur. As events reach the top of the queue, they are passed to the Event Steering Logic. The Steering Logic is responsible for routing each event by type to the Pre-Conditioning Logic, where calibration factors specific to each edge type are applied.
For example, drive edges behave differently when switching between logic levels than when switching in or out of tristate. The DUT-cycle timing architecture keeps track of an event history for each channel. This not only allows preconditioning of channel logic states for I/O switching, but also supports selection of different calibration factors for each switching condition.
Calibrated events then are forwarded to the Linearity Lookup Table for final accuracy corrections.
SiGe for Performance
Many factors contribute to ATE timing accuracy, from the fundamental timing-system architecture to the final physical interface from the DUT to the tester pin electronics. Some of these factors yield to careful design while others can be compensated for as part of system calibration.
Given the density of CMOS and the operating speed of SiGe, real-time adjustments now can be made for nonlinearity present in the final timing verniers. Correction for timing-vernier errors is performed using a lookup table accessed at full speed for each edge type. Combined with the Pre-Conditioning Logic, errors that have been ignored in previous timing-system architectures can be measured and corrected.
Figure 4 (see June 2000 issue of EE) shows the effects of linearity correction on edge-placement accuracy. Since the digital portion of the timing system is referenced to a precise 800-MHz clock, accuracy is guaranteed at 1.25-ns intervals. Between those clock ticks, the event-generator analog circuitry takes over.
Analog circuits all exhibit some amount of nonlinearity. Careful design can reduce but not eliminate that effect. As part of the system calibration process, deviations from perfect linearity are measured for each event generator, and correction factors are entered into a lookup table.
At full speed during pattern execution, each programmed event time is modified with those corrections before being sent to the final timing verniers. As a result, the effect of event-generator nonlinearity is reduced to a very few picoseconds.
Summary
Testing SOC devices will require a new level of performance from ATE. Every core will come with some level of test IP, but since no standards exist, levels of testability and techniques will differ widely. Some cores will be completely testable using scan methods; many will need to be tested at-speed. Some cores can be tested independently from the rest of the SOC while others must be tested as part of the functionality of the overall device.
Fortunately, there is a solution. Innovative, high-performance ATE timing-system architectures now are possible thanks to technology that was unavailable until very recently. If properly used, high-density submicron CMOS and SiGe high-performance mixed-signal capabilities support an unprecedented combination of speed, flexibility, and accuracy.
High-speed ATE timing systems historically have behaved like drag racers, very fast but traveling only in a straight line. The new DUT-cycle timing architecture performs much more like a Formula One car—very fast and extremely maneuverable.
New Technology in
SOC Test
The Catalyst T-Series, nicknamed Tiger, is a system-on-a-chip (SOC) test system with 1,024 digital pins; digital data rates up to 1.6 Gb/s; and full spectrum, high-accuracy analog test capability. It provides the high-speed test flexibility needed for high pin-count/high-performance SOCs used in data storage, transport, and processing applications such as disk drives, network switching, chip sets, and PC graphics.
The ATE timing-system architecture combines high-density submicron CMOS and the mixed-signal capabilities of IBM’s SiGe. This approach enables DUT cycle-timing programming where test waveforms are based on DUT requirements and not constrained by the test-system’s vector instruction rate.
By integrating 1,024 digital channels into the test head, the Catalyst T-Series provides data rates of 1.25 Gb/s (1.6 Gb/s differential) needed by high-speed, low-voltage data links typical in Internet switch and PC applications. The flexible waveform capability supports two independent time domains with timing, waveform, and period switching on the fly.
Each 32-channel test-head card contains per-pin resources including PMUs, pin electronics, pattern memory (up to 128 M x 3 bits), and a 1.6-Gb/s timing system. Each card also has a memory test controller with 16 Mbits of fail capture and 384 Mbits of source/capture/scan memory.
The T-Series includes a zero-time FlexDSP architecture and full differential analog instrumentation. DSP calculations at 15 billion operations/s perform sample-rate conversion and filtering in real time, resulting in 15-MHz bandwidth and -120-dB distortion. Options include the LFAC 1.2-MHz source and digitizer for DSL device testing; the VHF2400 2.4-GS/s, 10-bit arbitrary waveform generator and VHF 1-GHz digitizer for 100/1,000Base-T networking test applications; and a time jitter analyzer for very high-throughput PLL production test.
Parallel Test Architecture
Powered by IMAGE software, the Catalyst family is designed for multisite test. Rather than place a local DSP processor in each instrument, Catalyst improves test speed by first performing parallel data capture and move simultaneously and then processing the data centrally in the background while the next test is executing. The T-Series has a second pattern generator that splits the system into two independent machines, each with its own digital clock. Each 32-channel test-head card can be independently assigned to either of the two pattern generators.
Analog instruments also can be assigned and synchronized to either pattern generator. For asynchronous or fractional bus test, the two-clock system means easier programming because unrelated frequencies can be set exactly instead of through multiple, time set-based solutions. The second pattern generator supports parallel cell test so unrelated cells of an SOC device can be tested simultaneously. For multisite test, the second pattern generator allows devices to run fully asynchronously.
Catalyst T-Series software tools combine pre-silicon simulation, test-program generation, and device characterization. The VX Test Simulation software provides closed-loop simulation of the test environment.
The tester’s DUT cycle-timing system simplifies the CAE interface, allowing programmers to write in native device terms instead of a tester waveform palette language. The auto-debug digital development software (new with IMAGE V7.0) views problems from several angles while maintaining a close coordination among the debug tools. Detailed DUT and test information such as pins, levels, vectors, and timing is automatically transferred between tools. The Teradyne/LogicVision BIST Access Tool controls internal BIST circuits for both production-level pass/fail tests and detailed structural diagnostics.
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For more information, see “Benefits |
About the Author
Eric Larson is the digital technical marketing manager in the Multimedia Group at Teradyne’s Industrial/Consumer Division. In 21 years with the company, he has worked in technical marketing, technical sales, VLSI and memory test applications engineering, and product support. Teradyne, 880 Fox Lane, San Jose, CA 95131-1685, (408) 451-3410, e-mail: eric.larson@teradyne. com.
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June 2000