Reducing the Cost of Test in 2003

This year, there are many more ways being developed to reduce the cost of test than there are ATE companies. In anticipation of the elusive economic upturn, recently introduced testers and updates to existing ones continue to reduce the cost of test while simultaneously addressing more stringent technical requirements. And, there are many other innovative ways in which increased value is being delivered.

Several manufacturers of so-called big-iron testers have standardized on single platforms. This approach alters the buy/depreciate/obsolescence equation by ensuring future upgrade compatibility with legacy testers and test programs. In addition, greater circuit integration in instruments for automated test has helped to lower production costs, resulting in higher performance at prices comparable to those of earlier, slower models.

Higher numbers of pins are required for new system-on-a-chip (SOC) packages, but a greater pin-count also facilitates parallel test of multiple devices. The vice president of technology at LTX, Neil Kelly, commented that some customers now are specifying multiple-site test on the initial purchase orders. In previous years, the multisite capability was added later as production volume ramped up.

Design for testability (DFT) generally relates to IC design, but it also affects ATE. Testers that are DFT-aware integrate built-in self-test (BIST) resources into the ATE architecture. Virtual tools that access the on-chip BIST circuitry are seamlessly merged into the ATE software. There is no operational distinction between the use of these tools and instrument hardware and software within the actual tester.

A new class of DFT testers may drastically reduce the cost of test. Rather than perform functional testing by accessing all of an IC’s I/O pins, a DFT tester uses the SCAN port connections. If an IC design has made extensive use of DFT techniques, there may be no need for more than a DFT tester in production. Teseda, a manufacturer of DFT-focused ATE, forecasts an initial use model that combines a DFT tester at wafer sort with conventional ATE performing final functional tests on packaged parts.

Many companies have their own views of what constitutes an open architecture (OA). But without a single definition, the economy of scale promised by OA proponents won’t occur. Nevertheless, the Advantest-led Semiconductor Test Consortium (STC) continues moving forward, and at least one ATE company has separately announced a platform with an OA.

The problems are more economic than technical. How should OA ATE be configured if it is to be economically competitive with existing proprietary solutions across the range of price points presently served? An OA can be designed and all the software and hardware interfaces specified. Third-party instrument makers and software developers can provide products that will operate in such an OA ATE. But, will it be profitable for them to do so?

Single Platforms

The use of a single, scalable platform has many advantages from a manufacturer’s point of view. Within limits, such an architecture can address a wide range of speed and complexity requirements without redeveloping the tester chassis, power supplies, system software, and user interface.

“The Agilent Technologies 93000 SOC Series ATE is a single, scalable platform,” said Gordon DeWitte, an Agilent product marketing engineer. “It increases asset utilization by covering a range of applications, simplifies our customers’ manufacturing floors, and provides a long lifetime for the asset because of the product’s expandability.

“Port scalability allows a few high-speed channels to be added to a low-cost tester, matching the tester capability to the application requirements and minimizing cost. In addition to multisite test,” he continued, “the 93000’s concurrent test capability provides significant test time savings. The tester has up to 64 independent ports, yielding a very high level of concurrent test.”

Additional product features include background processing to speed up measurement time, a test processor-per-pin architecture to reduce setup time, and a wide selection of instruments to support applications from DC to RF. The tester also can perform test-vector compression/decompression to minimize pattern memory requirements.

LTX recently introduced the Model HFi, the latest tester built on the Fusion platform. It uses the same architecture and operating software as previous Fusion testers, but the hardware performance has been significantly improved to cope with more stringent SOC test requirements.

Much of the tester’s circuitry has been integrated, resulting in an 85% reduction in IC count. Four digital channels are controlled by a large CMOS ASIC in combination with two GaAs timing chips, two dual-channel bipolar driver/receiver chips, and a number of RAMs. The custom chips include glue logic, so the physical size of the circuitry really does shrink dramatically. As a consequence of the chip design and short path lengths, the Fusion HFi achieves a 2.5-GHz data rate per pin.

Equally as important as speed, the new hardware deals with source-synchronous SOC designs. In a traditional synchronous system, a single clock is distributed with as little skew as possible across the clock tree structure. Timing tolerances may become so tight in large and very fast designs that zero-skew clock distribution proves to be an impractical objective. Instead, a source-synchronous design can be used that distributes the clock with the data.

In a multidrop backplane design, for example, each daughter board would receive data relative to a specific clock signal. This clock is associated with the received data and not necessarily in phase with clocks on other daughter boards.

In a comparison of synchronous and source-synchronous systems, Fairchild Semiconductor developed an example that showed a 150% speed improvement. Using a private clock version of a source-synchronous system, a maximum data rate of 142.8 MHz was possible vs. 59.9 MHz for a traditional synchronous approach.¹

In a complex SOC, source-synchronous clocking may be used to achieve high-speed operation of several separate data ports. In this case, each port corresponds to a separate clock domain. The tester clocks must run as slaves to the individual port clocks rather than as independent clock sources. This type of operation is aided by the variable clock speed element of the Fusion architecture.

While the single-platform strategy has some attractive benefits, it is not the approach being taken by all ATE manufacturers. Phil Smith, a strategic marketing manager at Teradyne, explained that the company develops separate models to serve distinct market segments.

Although it makes sense to collapse as many products as possible into a smaller range with common parts and software, Mr. Smith explained that, in Teradyne’s view, a single platform is too restrictive. “The goals of [having a single platform] are correct, but the single-platform approach carries infrastructure baggage and configuration problems that can drive up the cost of each tool, reducing the benefit. The fact that about six times more market-focused systems were sold in the last five years than single-platform machines seems to bear this out.”

In Figure 1, the importance of performance, time to market, and cost of test is shown in relation to tester characteristics and types of devices being tested. The large variation in the curves is the reason that single-platform testers must be very flexible. Alternatively, Teradyne has chosen to address significant market segments with more specialized machines.

DFT

“It is estimated that more than 95% of new designs use full scan DFT test techniques,” according to Peter Hwang, director of marketing at Inovys. “This shift toward structural test is dictated by the increasing complexity of the designs and time-to-market pressures requiring faster product validation and release to production.