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NXP's i.MX95 is a high-performance system-on-chip (SoC) family that targets automotive as well as medical and industrial applications. It includes an array of Arm cores including up to six Cortex-A55s in the application domain plus real-time Cortex-M7 and Cortex-M33 cores. The real-time cores occupy safety-domain islands that can be used for various functions independently of the application domain.
The chip family also incorporates the eIQ Neutron NPU (Fig. 1). The Arm Mali GPU provides display support. I talked with James Prior, Manager of Advanced Edge Processors, about the i.MX95 and its application space.
The i.MX95 is divided into multiple domains that isolate functionality such as real-time support or security (Fig. 2). The NXP SafeAssure design support allows for creation of solutions that meet ASIL B and IEC61508 compliance. Up to six Arm Cortex-A55 cores make up the application cluster. A Cortex-M7 addresses real-time support while the low-power Arm Corex-M33 core targets safety.
The EdgeLock Secure Enclave hides its own core for managing security functionality and storage. The LPDDR5/4X memory interface handles real-time memory encryption as well as inline memory correction.
Graphics is based around the Arm Mali GPU. It includes a real-time blend engine and is combined with the NXP image signal processor (ISP) that supports RBG-IR and MIPI-CSI with up to eight virtual channels. The video processing unit (VPU) handles up to 32 video streams.
Also included in the Flex Domain is the eIQ Neutron neural processing unit (NPU) that accelerates machine-learning (ML) models, including CNN, MLP, RNN, LSTM, and TCN. The eIQ ML Software Development Environment provides tools for taking these models and compiling them for use with the NPU. The hardware performance scales from 32 ops/cycle to 2k ops/cycle. The software provides unified support for the NPU and NXP's range of ML platforms.
