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KLA-Tencor launches defect-inspection systems at SEMICON West

July 11, 2018

San Francisco, CA. KLA-Tencor today announced two new defect-inspection products, addressing key challenges in tool and process monitoring during silicon wafer and chip manufacturing at the leading-edge logic and memory nodes. In a presentation at SEMICON West, Lena Nicolaides, general manager, LS-SWIFT, and Jijen Vazhaeparambil, general manager, Surfscan/ADE, described the new Voyager 1015 and Surfscan SP7 and the advanced design-node challenges leading to the need for the new products.

The Voyager 1015 system offers new capability to inspect patterned wafers, including inspection in the lithography cell immediately after development of the photoresist, when the wafer can be reworked. The Surfscan SP7 system delivers improved defect detection sensitivity on bare wafers as well as smooth and rough films—essential for manufacturing silicon substrates intended for the 7-nm logic and advanced memory-device nodes, and equally critical for earliest detection of process issues during chip manufacturing. Both inspection systems are designed to accelerate time-to-market for innovative electronic devices by capturing defect excursions at their source.

Device scaling, Nicolaides and Jijen Vazhaeparambil said, is leading to smaller pitches and smaller feature sizes, and multipatterning leads to more process steps and the possibility of more defects due to process variability. EUV may help, but it imposes significantly higher costs per scan and integration challenges. Consequently, it becomes more important to capture smaller yield-critical defects and to detect, fix, and monitor yield-killing defects at the source.

Nicolaides described Voyager’s role in the semiconductor ecosystem, commenting on challenges relating signal (tighter pitches and smaller feature sizes), fragility (due to thin resist materials), and noise (due to rough lines, for instance). The Voyager offers increased collection and new sensors to add more signal, shorter wavelength to provide high resolution, a switchable laser optimized for after-develop inspection (ADI), and oblique illumination and channel fusion to suppress nuisance signals and noise.

Vazhaeparambil said Surfscan has a role to play at the wafer manufacturer (to ensure that substrates are free of yield-killing defects), IC fab (to identify critical issues at the source to minimize yield loss), and OEM (to accelerate process and process-tool development and qualification). He cited several Surfscan SP7 key technologies, including a new sensor to reduce noise, peak power control to protect fragile materials, and a new image computer to provide high speed and sensitivity.

“With leading IC technologies, wafer and chip manufacturers have very little room for error,” said Oreste Donzella, senior vice president and chief marketing officer at KLA-Tencor, in a press release. “Critical dimensions of next-generation chips are so small that the minimum size of a yield-killing defect on bare silicon wafers or blanket-film monitor wafers has shrunk below the detection limit of available tool monitoring systems. A second key gap in the defect detection space has been reliably detecting yield-killing defects introduced early in the lithography process, whether 193i or EUV. Our engineering teams have developed two new defect inspection systems—one for unpatterned/monitor wafers and one for patterned wafers—that provide key capability for engineers to address these difficult defect issues rapidly and accurately.”

The first Surfscan SP7 and Voyager 1015 systems have been operating at leading wafer, equipment, and chip manufacturers worldwide, where they work together with KLA-Tencor’s eDR electron-beam review systems and Klarity data-analytics systems to identify process-control issues at the source. For more information about the two new defect-inspection systems visit the Voyager 1015-Surfscan SP7 launch information page.

About the Author

Rick Nelson | Contributing Editor

Rick is currently Contributing Technical Editor. He was Executive Editor for EE in 2011-2018. Previously he served on several publications, including EDN and Vision Systems Design, and has received awards for signed editorials from the American Society of Business Publication Editors. He began as a design engineer at General Electric and Litton Industries and earned a BSEE degree from Penn State.

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