Slash your IP design cycle time with design-stage verification

IP designers are under immense pressure to deliver high-quality products quickly. A change to the design flow that pulls signoff quality verification into the implementation stage allows designers to find and fix errors in smaller, faster iterations that ultimately cut the time to tapeout significantly. Learn more about Calibre design stage verification and how it can benefit your projects by visiting the Calibre design stage verification page.

Time is a valuable asset in the fast-paced world of semiconductor design, so IC designers save time by using intellectual property (IP) in their designs. As a result, IP designers and verification engineers face constant pressure to deliver high-quality IP blocks quickly while keeping costs in check. Siemens EDA’s Calibre® platform offers a strategic shift left approach that allows teams to perform verification earlier in the IP design flow. This shift left approach reduces costs and expedites the IP design cycle while preserving confidence in the quality of the IP.

The challenges of traditional verification
In traditional verification, physical, circuit and electrical signoff happens after the design’s physical implementation is complete. For IP (either hard, soft or custom), confidence in the signoff results is of paramount importance. IP providers do not want their customers finding issues in the IP later when in the full-chip context. But the complexity of IP blocks can extend the verification timeline and increase the chances of errors. This puts immense pressure on design teams to deliver quality IP within tight timelines and increases the importance of avoiding costly rework and project delays.

Figure 1 shows a traditional IP design flow through the Calibre signoff physical verification stage. Designers create the logic and perform simulation to ensure it will meet the functional and performance requirements. The design (for hard IP) is then physically implemented either as full custom, with memory compilers or through place and route tools. The physical layout is checked against foundry design rules in a process that requires write-out and read-in of GDSII or OASIS file formats between different tool environments. Any errors found trigger a series of iterations that continue until the design is error-free.

Figure 1. The traditional IP design flow from logic creation to final post-layout simulation.

This design and verification flow has worked well for decades, but for large and complex designs that strain engineering and compute resources and that also have faster time-to-market requirements, we need to adjust the flow to achieve greater efficiency, manage costs and reduce time-to-market while ensuring design quality and performance.

A shift-left strategy for design-stage verification
By moving verification to earlier stages of the design process, IP designers can identify and resolve issues sooner and within their physical design environments, resulting in significant cost and time savings. Key benefits include:

Early defect detection: Identifying potential issues early on can prevent costly rework later in the design cycle.
Reduced verification cycles: By integrating verification into the design process, engineers can catch issues as they arise, reducing the number of verification cycles needed.
Improved efficiency: Automated verification capabilities streamline workflows and improve overall efficiency.

The heart of a shift left strategy takes advantage of the fact that the IC design flow is not actually a linear process of discrete steps, where one stage completes before going to the next. Many aspects of the design are in play simultaneously. Much of the process can be compared to a symphony warming up. IP is just one instrument in the symphony. The design or integration happens in parallel with multiple design processes to produce the final system-on-chip (SoC).

Maximizing ROI
IC companies that buy external IP rely on the quality and performance of that IP, so failure to meet expectations directly impacts the market success of commercial IP companies. For the IP designers, using a single foundry-trusted verification tool suite ensures design rules are checked and errors corrected consistently and with signoff-level quality at every stage of the IP design flow.

The Calibre platform from Siemens EDA is used by all major foundries to develop new technology node processes. Over 90% of semiconductor design companies use Calibre for their signoff physical verification and design optimization. With Calibre design-stage verification, IP designers have access to the same advanced verification and optimization functions, plus the underlying rule decks and engines used by the Calibre platform for signoff verification. When IP design teams perform early design stage verification with Calibre, they can have confidence that design issues will be accurately identified and corrected with signoff-quality fixes (figure 2).

Integrating design-stage verification into your IP design flow can have a profound impact on your bottom line. Here's how it helps maximize ROI:

Faster time-to-market: Reducing verification cycles and catching issues early speeds up the overall design cycle, allowing you to deliver IP blocks more quickly.
Lower costs: Early detection and resolution of issues save both time and money, minimizing the need for costly fixes later in the process.
Enhanced IP quality: By verifying designs early and often, you can create higher-quality IP blocks with fewer defects, enhancing your reputation with clients.