Cadence is ushering in “the future for custom analog design” with Virtuoso Studio. The San Jose, California-based company said the new platform takes care of many of the challenges its customers face when it comes to the custom analog, mixed-signal, and radio-frequency (RF) designs that pervade modern chips. Virtuoso Studio gives them the ability to analyze and verify designs faster and more accurately, which is vital as the complexity of analog designs continues to rise.
With all of the improvements under the hood, Cadence said it can boost productivity threefold. The EDA tool also leverages machine learning to upgrade IP to more advanced nodes with relative ease.
The platform seamlessly integrates with a wide range of other Cadence software—including the Spectre platform for simulation, Pegasus for verification, and Allegro for system-level design—breaking down some of the traditional walls in the design cycle.
Users can access the company’s Spectre Simulation Platform, including Spectre X Simulator and Spectre FX Simulator, which allows for the analysis of large custom analog and mixed-signal designs. Spectre FMC Analysis is also part of the package.
Moreover, Virtuoso Studio is integrated with Cadence’s AWR Microwave Office for the first time, giving users access to software to assist with the development of millimeter-wave chips used in 5G devices.
Moving Up in the Fab
Cadence said Virtuoso Studio gives customers the same overall experience they’re accustomed to with its existing Virtuoso toolset. But in a bid to boost productivity, the platform adds more automation when it comes to placement of transistors on-chip and more advanced features for device routing.
As companies push the boundaries of chip design with the latest process technologies, it’s becoming a serious challenge to scale the different features of a modern chip and cram them onto a monolithic die.
While many of the most advanced process nodes at foundries are primarily designed with digital in mind, they’re rarely appropriate for the analog and other custom IP in modern SoCs. The discrepancy tends to create difficulties for even the most skilled designers.
Cadence said it employs AI to ease the burden for customers such as MediaTek that are moving to the latest process technologies, which forces them to navigate competing specifications for analog and digital. Customers can use Virtuoso Studio’s AI models to take existing IP inside a SoC, transform it for a more advanced process node, and then validate it to reduce time-to-market.
Other improvements under the hood help keep chip designs from running off the rails and facilitate faster interactive editing of the schematic of the design as well as its ultimate physical layout. For instance, to identify flaws in the physical design, it can run design rule checks (DRC) and layout versus schematic (LVS) directly from Virtuoso Studio. Multi-threading is used to run these in parallel with connectivity extraction and other workloads.
Analog IP in a Package
For Analog Devices—one of the semiconductor vendors supporting Virtuoso Studio out of the gate—co-design of the IC and packaging is key for 2.5D and 3D system-level product development.
Cadence said Virtuoso Studio solves many of the challenges that system-in-package (SiP) chips present to the likes of Analog Devices. The tool supports co-analysis of electrical and electromagnetic (EM) and system-level integration and verification, including power and thermal analysis, of everything from the ICs—dubbed chiplets in the context of 2.5D and 3D designs—to the package (or module) to the PCB.
Virtuoso Studio provides a single interactive environment for capture, analysis, and verification at the IC, package, and system levels, which is ideal when it comes to co-packaging silicon photonics with SerDes in a switch or plugging millimeter-wave antennas into a 5G RF module. These building blocks can all be based on different process design kits (PDKs) from the foundries used by its clients.
Furthermore, Virtuoso Studio can take advantage of cloud scalability to help engineers save time and resources in the run-up to submitting the blueprint of a chip to the foundry. It’s optimized for customers’ preferred cloud providers or ready for private cloud deployment.
Using the cloud is effective in cases when the complexity of a custom or analog chip design turns hundreds of simulations into thousands, said Cadence.
