1 The Tensilica Fusion DSP core is a configurable dualissue VLIW DSP Optional features include singleprecision floating point AES encryption and baseband bit operations

DSP Targets IoT Apps with Low-Power Operation

May 6, 2015

Cadence’s Tensilica Fusion DSP architecture targets IoT, wearables, and communication applications.

Cadence’s Tensilica Fusion DSP architecture is aimed squarely at new Internet of Things (IoT) applications, as well as wearables and communication apps. The dual-issue, VLIW platform (Fig. 1) is designed for low-power operation. The system is highly customizable with configurations generating a complete, customized Xtensa tool suite and runtime support package. The instruction-set architecture (ISA) is design for extensibility and a number of options are available as well, including support for multiple wireless protocols including Bluetooth Low Energy, Thread, and Zigbee using IEEE 802.15.4, SmartGrid 802.15.4g, Wi-Fi 802.11n and 802.11ah, 2G and LTE Category 0 release 12 and 13, and global navigation satellite systems (GNSS).

The core is a dual-issue, VLIW processor based on Cadence’s Tensilica HiFi 3 architecture. The VLIW features are only used when required to reduce code size and increase overall system efficiency. The MAC support can be configured for single 32- by 32-bit operation or dual configurations of 32- by 16-bit, 24- by 24-bit, and 16- by 16-bit.

In addition to the core, Cadence can provide a number of integrated modules. These include single-precision floating point support, AES-128 encryption, and baseband bit operations for MAC and PHY algorithm acceleration. There is also audio/voice compatibility with the Tensilica HiFi audio DSP architecture. The floating-point implementation runs in parallel with 64-bit load/store operations.

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