Latched Overcurrent Fault Detector Has Fast Response Time

For the PDF version of this article, click here.

The circuit introduced here is a simple and fast-responding overcurrent detector for protection of low-voltage applications. Unlike dedicated hot-swap controllers that impose a long startup delay initiated by undervoltage, this circuit provides protection only 150 µs after the input supply rises above 2.7 V. It also possesses a measure of inrush current limiting during power up, by virtue of the limited gate voltage on an external p-channel switch.

Fig. 1 shows the complete circuit of the latched overcurrent fault detector. After power is applied, the comparator output (C_OUT) is close to 0 V. The noninverting buffer formed by Q2 and Q3 ensures that the gate of Q1, a very low on-resistance, low-threshold, p-channel power MOSFET, is fully enhanced. The resulting current into the load is measured by a high-side current-sense amplifier, which converts the small voltage across the current-sense resistor (R_SENSE) into a scaled, ground-referenced output voltage at the OUT pin. That voltage, which is proportional to the load current, is further scaled at the input of the latched, noninverting comparator.

When the load current produces a voltage at C_IN (the junction of R1 and R2) that exceeds the comparator threshold voltage, the comparator changes state, causing the output voltage (C_OUT) to be pulled high by R3. As the gate-to-source voltage falls below the gate threshold, the p-channel MOSFET is shut down. The noninverting buffer Q2-Q3 ensures ample charging and discharging current into and out of the Q1 gate, resulting in fast switching.

The MAX4373 is the controller selected for a fast-responding, current-latching, current-limit detector circuit able to operate from 3.3-V supplies. The MAX4373 integrates all the elements required to produce such a circuit: a high common-mode differential voltage detector, a reference and a latching comparator with active low reset. Startup delay is typically 500 µs from application of V_CC, and propagation delay through the comparator is typically 4 µs.

When selecting the sense resistor value to ensure optimum gain accuracy (typically 1% to 1.5%), the voltage drop at the rated current should be in the range 75 mV to 100 mV for gain values of 20 and 50 (provided by the T and F versions of the MAX4373, respectively). R_SENSE = V_SENSE/I_LOAD where 75 mV > V_SENSE > 100 mV. P_Rsense = V_SENSE × I_SENSE.

The dynamic range of the output is also an important consideration. You should center the nominal output voltage (corresponding to the operating/detecting current) at one-half the supply voltage. Note that V_OUT max is 250 mV below the supply voltage at V_CC . Thus, for V_CC = +3.3 V, V_OUT nominal should be approximately 1.4 V. In this example, a MAX4373 with gain of 20 (T version) is suitable with a 70-mV sense voltage.

For a sense current of 15 A in this application, R_SENSE=4.6 mΩ, producing a 70-mV V_SENSE. Choose the nearest value of 4.7 mΩ. Tolerance for the Tyco-Meggitt RL73H is ±1% (F suffix).

Having set the current-detection amplifier, you should set up the comparator to provide a switching output voltage suitable for disabling the series power switch. A resistor divider connects the current-amplifier output to the comparator-positive input. For switching, the internally set threshold of 600 mV nominal (580 mV to 618 mV) must be exceeded by the positive input of the comparator.

The current through R1 and R2 should be greater than 150 nA, and less than 500 µA at the nominal output voltage of the current-sense amplifier. The comparator output sinks 1 mA with a saturation voltage of 600 mV maximum. R3, the gate pull-up resistor, is calculated from the following equation:

The external p-channel MOSFET is chosen with peak current, on-resistance and gate voltage as the key selection specifications, closely followed by packaging. On-resistance should be chosen so that the voltage drop at the rated current is approximately the same as the current-sense voltage. That value produces similar levels of dissipation in the sense resistor and the MOSFET.

The Si7485DP MOSFET from Siliconix has a 9-mΩ maximum on-resistance at V_GS = -2.5 V. This 20-V p-channel device was selected for its operation at low input voltages. The worst-case steady-state dissipation is:

At a 15-A load current and a 9-mΩ on-resistance, the Si7485DP operates 40°C to 50°C above ambient, so additional heatsinking is required according to the final application. In this example, the power switch has a gate-charge specification of about 60 nC. If a fast response is required, that value is beyond the drive capability of R3 and the low-power comparator output. A gate-drive buffer is therefore mandatory. As outlined above, Q2 and Q3 form a complementary emitter-follower driver that provides significant bipolar current gain into the gate of Q1. The transistors are chosen with good dc beta at medium collector currents of 500 mA to 1 A. Suitable choices are the Zetex FZT688B (npn) and FZT788B (pnp), packaged in SOT-223 outlines. Gate time = G_T = Q_GATE/I_PEAKinput.

The value of the current actually sensed depends on tolerance buildup due to the following:

Ignoring the sense-voltage tolerance, overall current-sense tolerance is close to ±10.8%. Detailed limits can be calculated using the following equation:

Using ±0.1% tolerance resistors for R1 and R2 reduces the error limits somewhat (approx ±1%), but the additional cost may not be supported by the end application.

Fast response to a fault and the subsequent current interruption is a key requirement. However, energy remaining in the power leads' distributed inductance can produce damaging voltage spikes. Some of that energy is absorbed by distributed capacitance in the load supply, but a fast-responding overvoltage clamp may be required to protect the MAX4373 from transients of 28 V or higher.

As a test of circuit operation, a current probe monitors load current at the input terminal (V_IN in Fig. 1). Load current (Ch4 in Fig. 2) is increased until it reaches the threshold and triggers the circuit. Response time is about 2 µs.

Acknowledgment

The author would like to thank Kevin Frick for his layout, construction and testing of the circuit shown in Fig. 1.