In 1999, Rob Dekker formed Verific, a provider of hardware-description-language (HDL) source code software. Today, Dekker and a team of dedicated engineers develop parsers and elaborators for SystemVerilog, Verilog, and VHDL that have been used as the front-end software for synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications.
Prior to founding Verific, Dekker was a software developer, manager, and director at Exemplar Logic, now part of Mentor Graphics. He was the architect and a primary developer of Leonardo, synthesis software used by field-programmable-gate-array (FPGA) designers. Dekker started his career with Philips Research in the Netherlands, where he worked on the testability of VLSI circuits. He graduated from Delft University of Technology, the Netherlands, with a Master of Science degree in electrical engineering.