Raju Rakha is lead ASIC design engineer in physical design at Open-Silicon Reserch Pvt. Ltd. India. He has more than six years of experience in physical design, STA and methodology in chip design and EDA. He also is involved in multiple hierarchical full-chip implementations on the latest technology nodes with design sizes in the range of 50 million gates. He has a BTech from NIT Durgapur and an MS in microelectronics from Manipal University.