RS-485: How To Correct The Bus Signal Polarity Of Cross-Wired Data-Links

The world is going crazy—or so it appears to be, at least in the industrial networks, such as RS-485, of emerging industrial countries.

First, the termination resistors in medium and long distance networks have disappeared just to save a few milliwatts, even though simply replacing a standard light bulb in a 40-W office lamp with an energy-saving one would have saved 200 times more energy than throwing 150 years of transmission-line theory out the window.

Next, twisted-pair cable, such as CAT-5 typically encountered in RS-485 links, has been replaced as a transmission medium by ultra-cheap, parallel lamp wire, significantly increasing the common-mode noise that damages bus transceivers and further reducing data-link reliability.

And most recently, cross-wire faults are occurring in the network cabling during installation. The increased use of inadequately skilled installers is forcing network designers to compensate for myriad possible installation issues as they design their bus node. To support these designers with a speedy development, options for bus signal polarity correction (POLCOR) are available.

The Concept

In POLCOR, the network controlling node (master) must define the correct signal polarity on the bus, while all other nodes (slaves) must adapt to this polarity (Fig. 1). The bus polarity can be defined through the master either via a training byte sequence or by establishing a bus failsafe voltage that’s present during bus idling.

The slave nodes then must detect a reversed polarity of the bus signal either by comparing the training byte with an internal code stored in the controller memory or by measuring the actual bus failsafe voltage. The second step is to correct for a possible signal reversal within the slave node by inverting receive and transmit data either by EXORING the binary data on the transceiver control side with logic 1 or by switching the transceiver bus terminals.

The Software Solution

A pure software solution allows for the use of standard components for the transceiver and controller and presents the most sophisticated and elegant solution (Fig. 2). This method requires the slave node to be loaded with the training byte during power-up. By default, all slaves are configured for operating in receive mode.

2. Polarity correction purely by software allows for the use of standard transceiver and controller components.

When the master sends the training byte, each slave controller compares the receive bit sequence with the initial bit pattern stored in its memory. If the comparison result is true, no further action is required. If not, the controller starts inverting receive and transmit data by EXORING a data byte with logic one (or high).

Mixed Software/Hardware Solutions

To minimize the software effort within the controller, modern transceiver designs have the XOR function integrated in the form of gates. But while pin compatibility with standard transceivers is commonly desired, the inverting control-input activating the XOR-gates (INV) typically replaces the receive enable input (/RE) of standard transceivers (Fig. 3).

3. Polarity correction using a modern transceiver with internal XOR gates requires the receiver section to remain active all the time.

A logic low at INV ensures non-inverted receive data at the receiver output R and non-inverted transmit data at the driver outputs, A and B. A high level at INV inverts the data conversion between bus input and receiver output and driver input and bus output.

If individual receiver control must be maintained, polarity correction can be accomplished with a standard transceiver by inserting an inexpensive dual XOR-gate into the drive and receive data lines (Fig. 4). Three I/O ports are necessary in this case. One is for inverting the data in transmit and receive, while the other two are for enabling and disabling the driver and receiver.

4. Maintaining individual receiver control requires a standard transceiver and a dual XOR gate.

The Hardware Solution

An alternative method to sending a training byte is the actual measurement of the bus failsafe voltage. This is the voltage between the A and B conductors when no driver is actively driving the bus. A bus failsafe voltage is established by implementing a resistive failsafe biasing network at the master node.

The voltage divider action between the upper and lower failsafe resistors (R_FS) and the termination resistor (R_T) must create a bus voltage that is greater than the receiver input sensitivity of 200 mV (Fig. 1, again). When the bus idles, the receiver outputs of correctly wired nodes then will present logic high, while the outputs of the cross-wired nodes will output low.

To distinguish between failsafe low and data low, a delay-logic that only latches a wrong polarity condition if the low level detected is of sufficient length must be implemented. Figure 5 presents a circuit that accomplishes this.

5. Polarity correction the hard way: Measuring the bus failsafe voltage requires the implementation of a bus idle time during data transmission.

When the receiver output R goes low sufficiently long, the R-C unit is charged until the input threshold of the following Schmitt trigger buffer is reached. The buffer output then creates a positive edge at the D-flip flop clock input, which latches the V_CC level at the D-input to its Q-output. When Q turns high, both XOR gates start inverting the data in receive and transmit.

To reset the D flip-flop during power-up or hot swap, the node’s power-on reset (POR) circuit controls the flip-flop reset-input.

The R-C time constant must be long enough to prevent prolonged low-data under correct wiring conditions from falsely triggering a polarity correction. For example, the simplified UART protocol in Figure 6 consists of a low-active start bit, followed by eight data bits, followed by two stop bits.

If the node is correctly wired and all data bits are low, the receiver output will turn low for a total sequence of nine bits. To prevent false triggering of the correction logic, the R-C delay must last for a minimum of nine bit lengths of the lowest data rate applied. But when accounting for data jitter, one should add a guard-band time, t_GB, of one or two bit lengths to extend the total failsafe time, t_FS.

The R-C time constant generally can be calculated via:

with N as the maximum possible number of consecutive low bits, GB the number of guard band bits, DR the lowest possible data rate in bits per second, V_TH-MIN the minimum positive Schmitt-trigger threshold, and V_CC-MIN the minimum supply voltage.

Conclusion

The search for great solutions to challenging problems often brings out the best in dedicated engineers. In today’s world, however, the definition of “challenging” allows for a wide range of interpretation. One culture or category of engineers sees an enormous accomplishment in making network installations foolproof by enabling the utilization of low-labor installers to further reduce development cost.

The opposing engineering mindset to this is paying attention to detail by ensuring correct network wiring during installation. In this case the elimination of simple human errors is a given matter of course and not open for discussion. The challenging aspect of a reliable network design rather lies in ensuring its robustness against external noise and potentially dangerous electrical transients.

Here the cost-saving effect can be seen in the long term by preventing network downtimes that otherwise could lead to costly product recalls.

References

For more information on RS-485, visit www.ti.com/rs485-ca.