Meeting the demanding performance requirements of today’s system-on-a-chip (SoC) applications, whether in high-data-rate telecom systems or high-quality audio and video equipment, requires extensive signal processing. Data converters are an essential element of the signal processing chain.
However, the performance of systems incorporating data converters depends, to a large extent, on the sampling clock’s quality. Uncertainty of the time instant when the analog-to-digital converter (ADC) samples the signal—defined as clock jitter—increases conversion noise, which reduces the overall system performance.
The effect of jitter on ADCs’ sampling error can best be handled by focusing on the frequency domain of the corresponding phase noise representation of jitter.
Several examples representing wireless communications applications will illustrate the sampling error mechanisms and their impact on the performance of ADCs in terms of signal-to-noise ratio (SNR). A thorough understanding of the frequency-domain mechanisms relating jitter to sampling errors will allow designers to better handle design tradeoffs and achieve the optimal system and data-converter performance.
Clock jitter is probably the most misunderstood specification in data converters. As data converters increased sampling frequencies and resolutions, they became more sensitive to external conditions. Clock timing quality is one of these conditions. The clock applied to the data converter determines the timing of the samples produced from the input signal. Basically, jitter describes the timing errors in the sampling operation caused by clock disturbances. Therefore, the clock must be treated as a delicate analog signal and any disturbances should be minimized.
Relating Jitter To Phase Noise
Data converters operate on the basis of sampling theory, which assumes the input signal is sampled periodically. If the time interval between any two samples is constant, the analog input signal will be reproduced exactly, as a sequence of digital words at the output. Any deviation or uncertainty of the time interval between two samples with respect to the ideal interval, defined as jitter, translates into sampling errors that degrade the signal quality at the ADC’s output.
The impact of the jitter (δt) on sampling is represented by the voltage sampling error (verror), and is expressed by Equation 1, where the jitter is multiplied by the time derivative of the input signal at the sampling time (kTs):
However, this time-domain treatment of jitter has some limitations because it attaches all the sampling error to the output signal even if part of it may be out-of-band and removed by filtering at a later stage. To account for this, you need a spectrum representation of the sampling error.
The spectrum of jitter is very difficult to measure directly, but measurement of a clock signal’s phase noise is quite straightforward. The phase noise (vclock), which appears as side lobes around the clock frequency in a spectrum analyzer, results from the clock’s phase modulation with the time-domain instabilities, or jitter:
where φ(t) is the phase noise in the time domain and FS is the clock or sampling frequency. Assuming that Φ(t) is small, vclock can be approximated as:
The second term of Equation 3 is the noise added by the phase modulation. The phase noise appears multiplied by a cosine at the clock frequency. It follows that in the frequency domain, the spectrum of the phase noise, φ(f), is convolved with the noise-free clock and appears as sidebands around its center frequency. The sampling operation is equivalent to the multiplication of the clock by the input signal, and the jitter-induced error is proportional to the derivative of the input signal, as in Equation 1.
According to the convolution theorem, multiplication in the time domain corresponds to a convolution in the frequency domain. Therefore, after sampling, the clock’s phase noise appears centered on the input signal frequency and is scaled by the ratio of the input signal to the clock frequency:
To obtain the in-band noise that will affect the SNR, or the SNR limitation due to jitter (SNRj), Equation 4 is integrated in power over the application passband (FMin, FMax):
Using Equation 5, designers can precisely estimate the impact of phase noise on the ADC’s performance, taking into account the signal’s spectrum distribution. But before providing a few examples, the characteristics of the phase noise for the two most common clock generators—oscillators and PLLs—should be understood.
Oscillator Phase Noise
An oscillator’s phase noise consists of two main regions. The larger region is due to thermal noise and is characterized by sidebands falling inversely proportional to frequency offset (Fig. 1). In a log plot, their slope is -20 dB/decade. At low frequency offsets, the smaller region, with a slope of -30 dB/decade, is due to up-conversion of 1/f noise.
The oscillator’s amplitude noise appears as a flat curve. Contributors to the amplitude noise are mainly buffers in the signal path. The oscillator itself has very low amplitude noise due to its own mechanisms for amplitude stabilization. On a spectrum analyzer, the oscillator’s output is a combination of both noises, as illustrated by the dashed curve in Figure 1.
PLL Phase Noise
A PLL behaves as a low-pass filter for the phase noise of the input clock reference and a high-pass filter for the locked voltage-controlled oscillator (VCO). Most common implementations have a second-order transfer function. In the case of the input clock reference, the PLL also applies a gain, M, equal to the ratio of output frequency to input frequency.
Typically, the input clock comes from a crystal oscillator and as such has very low phase noise, even after amplification by M. This noise will impact the output phase noise only at very low offset frequencies. The locked voltage-controlled oscillator (VCO) phase noise is often relatively large, especially if the circuit is built as a ring oscillator and most of its energy is at low frequencies (Fig. 2).
The PLL’s internal blocks, especially the phase detector, generate additional noise that is transferred to the output with a low-pass transfer function similar to the input clock reference. Figure 2 shows the resulting phase noise spectrum at the output. The curve for the locked VCO phase noise gets filtered down by a steep 40-dB/decade slope below the PLL loop bandwidth. Therefore, the -20 dB/decade is on a downward slope below floop. Even the 1/f region is pushed down by the loop’s filter action.
The phase noise of the input reference clock is relevant only at very low offset frequencies. The phase-detector and charge-pump noise may become the dominant phase noise contribution below the PLL loop bandwidth. At high offset frequencies, the amplitude noise dominates and generates a flat region. The dashed curve in Figure 2 shows the combined spectrum at the PLL’s output.
Noise from the supplies or the substrate can also contaminate the PLL output. This noise is typically generated by the actual activity in the chip and can show up as spurs on the phase noise spectrum. An example is illustrated in Figure 2 by the vertical line at floop.
Example Applications
The following application examples illustrate the sampling error mechanisms and their impact on the SNR and, consequently, on the ADC’s performance. Besides generic sinusoidal signals, the examples cover sub-sampling, the presence of interferers, orthogonal frequency-division multiplexing (OFDM) modulated signals, broadband noise, and clock division.
For simplicity, the same clocking system will be used in all the examples. The master clock is produced by a PLL and has the phase noise spectrum shown in Figure 3 for a clock frequency of 1 GHz. The noise density is flat within the band, corresponding to similar noise contributions by the VCO and the phase-detector/charge-pump. The reference clock’s phase noise (the dotted line in the low-frequency corner) will be ignored because it is often below the slowest relevant signal rates and therefore does not impact system performance.
For this simple clock, the total phase noise power can be easily calculated by integrating the area of the solid curve (and multiplying by two for double-sideband). Taking the square root provides the rms phase noise (φtotal):
The corresponding jitter is:
Sampling Of Generic Sinusoidal Signals
The first example is an ADC sampling a sine wave with a clock frequency of 100 MHz. This clock is obtained from the 1-GHz master clock described above using a divide-by-10 circuit (Fig. 4).
The divider will add some flat phase noise, such as the horizontal line in Figure 2. However, assuming that the noise is low enough, it can be ignored. Also, the input signal bandwidth is limited to 25 MHz and a digital filter after the ADC removes all the energy above that bandwidth.
The 100-MHz clock will have the same jitter as the 1-GHz master clock. Its phase noise will have the same spectrum shape but scaled down by 10, or shifted down by 20 dB, resulting in a total phase noise of 0.0056 rad. rms.
The worst-case situation is an input sine wave with an amplitude equal to the ADC’s full-scale specification and a frequency that is near to but just below 25 MHz, so most of the phase noise will stay within the digital filter’s pass band. So, assuming the frequency is 24 MHz, SNRj can be calculated using:
where Fs is the ADC sampling frequency, 100 MHz, equal to the master clock divided by 10.
The corresponding phase noise, ΦFs, is equal to the master clock phase noise scaled down by the same factor of 10. Note that the end result would be the same if the same input signal had been sampled at the master clock frequency of 1 GHz. This is because the division factor, 1/10, cancels in the numerator with the denominator. The SNRj is, in fact, a function of only the master clock phase noise and the ratio of its frequency to the input signal’s frequency. SNRj is independent of the actual sampling frequency.
In this example, the integral limits include most of the phase noise energy because the signal frequency chosen is below the passband limit by only 1 MHz. A simpler derivation of SNRj can then be obtained by taking the total phase noise of the master clock obtained in Equation 6 and scaling it by the ratio of the input frequency to the master clock frequency:
If the maximum signal amplitude has some headroom below the ADC’s full-scale specification, the headroom must be added to the result. For example, to allow for sudden changes in signal strength in radio equipment, the signal amplitude is adjusted to main some margin below the ADC full-scale level.
This example illustrates some key points regarding the effect of clock phase noise on the SNR of ADCs:
- The actual sampling frequency is not relevant. What is relevant is the master clock phase noise and its frequency ratio to the signal.
- The worst-case situation is a maximum amplitude sine wave just below the passband limit so most of the convoluted phase noise is in-band.
- Any headroom in the ADC will directly improve the SNR result.
Sub-Sampling
Some applications, such as direct intermediate frequency (IF) sampling in certain radio architectures, use a sub-sampling technique. In this technique, the input signal is near one of the clock harmonics. After sampling, it’s shifted to baseband by aliasing.
This example uses an input signal frequency of 302 MHz. After sampling with the 100-MHz clock, it gets shifted to 2 MHz due to aliasing with the third clock harmonic, 300 MHz (Fig. 5).
Using Equation 5, SNRj is:
This is 22 dB worse than the generic sinusoid example and clearly shows that systems operating in sub-sampling are much more sensitive to clock jitter. In fact, the effect is directly related to the input signal frequency and independent of the actual sampling frequency.
Interferer Situations
Next, consider a situation in which the in-band received signal is very weak, such as the signal received by an antenna in a radio receiver. For example, assume it is 60 dB below the ADC full-scale level. The passband is 25 MHz, but there are strong interfering signals out-of-band. These interferer signals can be as strong as -6 dBFS, meaning that there is 6 dB of headroom to the ADC full-scale. Also assume that the closest interferer to the passband is at 26 MHz (Fig. 6).
After the ADC, this interferer is completely removed by the digital low-pass filter in the example. Due to the phase noise convolution process, however, some of the sampling noise on this interferer will fall in-band and affect the SNR. More specifically, the phase noise above 1 MHz will offset the frequency on the lower sideband. Integrating Φ2(f) for offset frequencies above 1 MHz yields the corresponding noise that falls in-band:
Note that this time there is no multiplication by two because only one sideband contributes to the noise.
SNRj, already including 6 dB for the headroom, is then:
which results in a SNRj of just 18 dB on the -60-dBFS weak input signal.
OFDM Modulated Signals
In telecommunications, many systems use modulation techniques that generate a broad, flat spectrum. For example, OFDM consists of multiple (often more than 1000) sub-bands tightly packed side by side so they completely fill the available channel bandwidth. Therefore, these systems are very bandwidth efficient. They are also resistant to interference because only the sub-band masked by the interferer is lost and it may be recovered by forward error correction. Examples of systems using OFDM are WLAN, WiMAX, digital TV, Universal Mobile Telecommunications Systems (UMTS), and Long-Term Evolution (LTE) mobile communications.
This type of system is harder to analyze for the effect of jitter on the sampling clock because there is no single sine-wave carrier to convolve with the clock phase noise. Instead, it is a multi-carrier signal—one carrier for each sub-band.
Also, one characteristic of OFDM modulation is its large peak-to-rms ratio, typically 15 dB. As a result, OFDM needs relatively large headroom from the ADC full-scale level. The SNR derivations used a sine wave that has a peak-to-rms ratio of 3 dB. Therefore, additional headroom of 12 dB must be considered for OFDM modulated signals.
Finally, phase noise at frequency offsets below the carrier separation produce a common rotation to all the carriers and can be compensated with signal processing. Therefore, only the phase noise at offset frequencies above the carrier separation is relevant.
For simplicity, consider an OFDM signal as multiple sine waves, one for each carrier. If there are 1000 sub-bands in a 10-MHz channel at baseband (between -5 MHz and +5 MHz), the power in each carrier is 1/1000 of the signal power (-30 dB) because the carriers are uncorrelated with each other. The signal power is below the ADC full-scale by the headroom, 15 dB, to accommodate the peak-to-rms ratio. Therefore, each carrier is at -45 dBFS (Fig. 7).
For proper demodulation of this signal a certain SNR must be achieved. Considering QAM-256 (quadrature amplitude modulation), the SNR must be better than 35 dB. The clock phase noise will be convolved with each carrier scaled by the carrier frequency. Normally, the carriers’ separation is small and below the PLL loop’s bandwidth, and the channel width is much larger than the PLL bandwidth.
With a clock phase noise spectrum similar to that in Figure 3, most of the convolved noise energy for each carrier stays within the channel, scaled by the carrier frequency from 0 to 5 MHz. The average noise power per carrier occurs for the carrier at the frequency:
To obtain the total noise in the channel, the 1000 carriers must be added, which adds 30 dB. But since each carrier power is also 30 dB below the total signal energy, these terms cancel out. The resulting SNRj is, then:
Based on this result, two conclusions are evident. One is that the SNR is independent of the number of carriers. Second, the resulting SNR is well above the required 35 dB, showing that OFDM modulation is very robust to sampling jitter, being limited instead by nearby interferer situations as described above.
Broadband Phase Noise
Another example is a situation in which the clock signal is routed through a large digital core with insufficient isolation precautions. This can happen in a large SoC if the clock distribution is not carefully planned. The result is a clock signal corrupted with broadband noise from the several gates being crossed, supply and substrate noise, and crosstalk from neighboring lines.
The bandwidth of this noise extends well above the clock frequency and is limited by the digital gates’ speed (Fig. 8). After sampling, the high-frequency components of the phase noise fold back into the Nyquist band (0-to-Fs) due to aliasing and can become the dominant source of phase noise compared with the low-frequency components.
In this example, only the band from 0 to 25 MHz will be captured due to the digital low-pass filter following the ADC. Therefore, half the broadband noise is removed due to the oversampling used in this ADC. In sigma-delta ADCs, the oversampling is much higher, in the order of 100. In these systems, the robustness of the ADC to broadband phase noise is very good because approximately 99% of the noise is removed in the decimating digital filters.
Clock Divider
As noted, the phase noise is affected by the division factor in the frequency division process (assuming the divider is ideal and adds no noise). However, that does not include the effect of aliasing.
In fact, the noise above the divided clock frequency is aliased and is folded down. Therefore, the high-frequency flat portion of the phase noise (the flat line in Figure 9) is scaled with the square root of the division ratio. This high-frequency phase noise is often negligible compared with the low-frequency part, but for large division factors it can become significant and affect the application.
By understanding the frequency-domain mechanisms of jitter-induced sampling errors and their impact on the SNR of ADCs, designers will be better able to optimize the design trade-offs in their high-performance systems.