Using the circuit presented here, you can construct a very inexpensive AGC amplifier with the following features: a dynamic range greater than 50 dB; negligible distortion to the output waveform; fast attack and slow decay; an adjustable output level from 0 to 1.2 V p-p; operation from a single 5-V supply; less than 1-mA current drain; and low cost (uses one half of a dual 8-pin op-amp package at less than $2.50 in parts). Better yet, if you need a second channel, the remaining half of the op amp can be used for that circuit.
Referring to the diagram, Q2 (a Pchannel JFET), coupled with R2 and the equivalent resistance of R3 and R4, form a voltage divider to the input signal source. With input levels below 40 mV p-p, the input is evenly divided between R2 (120k) and R3 ¦ ¦ R4 (120k). The output amplitude of U1A isn’t large enough to turn on Q2, which acts as a positive peak detector. The gate of the JFET is pulled to +5 V, pinching its channel off and creating a very high resistance from drain to source. This essentially removes it from the circuit.
At input levels above 40 mV p-p, Q1 is turned on at the positive peaks of the output of U1A, lowering the JFETs gate to source voltage. The channel resistance decreases and attenuates the input signal to maintain the output of U1A at approximately 1.2 V p-p.
The circuit, as shown, was tested with a sine-wave input ranging from 300 Hz to 30 kHz at 40 mV to 20 V p-p, a 54-dB range. It maintained the output level at 1.2 V p-p, ±0.5 dB, with no visible distortion when comparing it with the input waveform. With a 40 mV to 20 V p-p input signal, the amplitude of the signal across the JFET (VDS) measured less than 20 mV p-p.
Other JFETs with VGS(OFF) of 5V or under, such as the 2N5019 or 2N5116, should work equally well in this circuit, although they haven’t been tried. To use JFETs with higher VGS(OFF), such as the 2N3993 (it was tried and worked equally well), increase the supply voltage to 12 V.
