Selecting the right high-speed analog-to-digital converter (ADC) can be difficult with all the alternatives and suppliers to choose from today. As you narrow your search, the choice often comes down to picking a buffered or unbuffered (switched-capacitor) type converter. Applications that are size and power restricted typically lean toward the unbuffered type. In either case, there are many papers out there that warn of troubling analog input interfaces, particularly at higher IF frequencies.
The fundamental end goal when using an ADC in the signal chain is to realize the best dynamic range specifications of noise (signal-to-noise ratio or SNR) and linearity (spurious free dynamic range or SFDR) in your design and ultimately at the system level. This discussion will establish the differences (pros/cons) between buffered and unbuffered ADCs. We will then discuss kickback, commonly called charge injection, from the raw unbuffered ADC internal sample network as well as how to drive an unbuffered ADC. Finally we will wrap up with the special analog input interface design requirements that are needed for crafting the proper anti-aliasing filter (AAF), showing a specific example.
Do I Need To Use A Buffered ADC?
There are key differences between buffered and unbuffered ADCs (see “High-Speed ADC Input Impedance” at www.electronicdesign.com). The advantages of the buffer are relatively straightforward. The buffer isolates the analog interface circuits from the internal switched-capacitor sampling operation. This presents the ADC driver with a controlled input impedance with greatly reduced transients commonly called kickback. Kickback or charge injection is the residual charge that is thrown back onto the input signal as the ADC’s internal sampling switch opens and closes.
These “buffered benefits” will simplify the analog interface design to some degree and may allow for higher input bandwidth. However, the drawbacks of the buffer are less obvious, but still present. The buffer usually requires a higher power-supply voltage, so it also imposes additional power-supply design issues. The ADC noise and linearity are also impacted, so the overall ADC design is significantly impacted in terms of power.
At the system level, the input of most high-speed ADCs is driven with an amplifier. So, the buffer’s power is somewhat redundant in common signal chain applications. If the analog interface circuits and amplifier are set up to drive the sampling network directly, rather than having a buffer, then the overall system can be better optimized. The question is how to deal with the raw sampling capacitor’s charge (kickback) presented to the driver circuit.
Removing the buffer is the tradeoff most system designers lean to because of this extra power savings, but they then have the daunting task of coming up with a realizable analog interface between the converter and amplifier. Fear not, as even though unbuffered converters’ impedance moves with the sampling state, between track mode and hold mode, and over IF frequency, the design will work in the final application. You just need to follow some careful considerations when designing with unbuffered ADCs.
Understanding Anti-Aliasing Issues
ADCs are an interesting analog function in the signal chain. Whether the chosen ADC is buffered or unbuffered, it requires a proper AAF design between the driver amplifier and the converter to lower the broadband noise and spurious. The ADC has some very unique properties versus conventional linear blocks (i.e., mixers, amplifiers). One of those issues is aliasing.
Aliasing is the “folding” of all frequency content into baseband or the first Nyquist zone. This is a problem if there are unwanted spurious and noise outside the desired signal bandwidth (target Nyquist zone). To prevent this, an anti-alias filter is normally employed just prior to the ADC’s input. The driving amplifier, anti-alias filter, and sampling network, internal to the ADC, become a tightly woven system that can be optimized to meet most applications very efficiently. You just need a little know-how to get it right.
The first step is to determine the anti-alias filter requirements, which include the stop band rejection profile and the passband ripple requirements. These requirements are normally set by any content that is out of band and must be prevented from “aliasing” into the band of interest. The goal is to determine the minimum filter order that can be implemented and still meet the requirements. This will minimize components and overall system complexity. For this discussion, a passive LC filter will be assumed.
Once the filter is defined, the next step will be to set the impedance of the analog interface. Lower impedance is beneficial for the ADC as it presents the sampling network with lower drive impedance, but this is more difficult for the drive amplifier. This is a critical design decision. Most driver amplifiers are set up to drive approximately 75 Ω (single ended), so this is a good starting point for the AAF design.
The LC filter should have a shunt capacitor at the ADC input regardless of order or type. This capacitor is critical to the filter/ADC interface. The shunt capacitor acts as the first buffer to any charge kickback from the unbuffered ADC. The larger the capacitor, the better the charge kickback is suppressed and the designer will improve the ADC drive. Keep in mind that impedance scaling within the AAF can be done to optimize the ADC performance and/or amplifier performance.
The other factor in driving an unbuffered switch capacitor high-speed ADC with an LC filter is the Q of the filter’s output impedance. The filter is driving the sampling network of the ADC, as such; the output impedance is an integral part of the ADC’s drive impedance. If the Q of the filter driving network is too high, then the charge kickback of the ADC’s internal sampling network will induce ringing at the analog inputs. This ringing profile will create additional distortion mechanisms if it does not dissipate within one clock cycle.
Most ADC analog interface designs are really lumped element networks rather than matched systems. This “IF strip” becomes the transition between “matching” and a lumped element analysis and the converter’s “usable” bandwidth, shunt capacitance requirements, de-Q’ing, wavelengths, and trace length limits. Understanding these variables leads to several different AAF tradeoffs and design methodologies to consider.
AAF Design Example
Most analog interfaces can be designed with LC anti-alias filters after the driver amplifier. The input frequencies are such that the system can be analyzed as a lumped element circuit versus an impedance matching problem. As long as the routing distance is less than one-tenth of the wavelength of the analog input, then a lumped element model is sufficient. Even significant routing distances don’t usually require impedance matching. However, longer routing distances do impose other problems.
The board trace routes introduce parasitic inductance and capacitance into the LC filter. This can be accounted for in the filter design by altering the filter component values to account for the printed circuit board (PCB) parasitic. The critical issue is to keep the final shunt capacitance in the anti-alias filter as close the ADC input as possible. This will minimize any inductance in the sample network that can induce ringing due to the clocked nature of the analog interface.
To illustrate the concept, consider a simple second-order LC AAF design with a series inductance, shunt capacitance, and termination resistance yielding the following transfer function for the filter section.
This has the generic second-order form of:
If we equate coefficients of the two transfer functions, we find:
For most applications, the bandwidth is a fixed design parameter as well as the filter type (e.g., Butterworth in this case). These two factors alone do not lock in the filter design. The final parameter is impedance level, that is, the filter can be scaled in impedance to favor the ADC drive or the amplifier loading.
Let’s assume a bandwidth of 200 MHz and a second-order Butterworth response. With an amplifier designed to drive a 150-Ω load, we would have R = 150 Ω; L = 155 nH; C = 4 pF. However, if 4-pF shunt capacitance was insufficient to buffer the charge kickback, then the AAF impedance could be scaled down at the expense of loading the amplifier and vice versa.
There are additional limitations to the AAF from practical considerations such as the board’s physical layout. For example, it may not always be possible to locate the amplifier and ADC extremely close. The board routing then becomes part of the AAF design. The trace routing will add additional series inductance and also capacitance, which will affect the filter’s response.
This can be accounted for in the component selection to reduce the inductance value and allow the board trace to account for part of the actual AAF inductance value. The most critical piece of the design is then to place the shunt capacitance as close as possible, without breaking manufacturing rules, to the ADC inputs as this capacitance is “buffering” any charge kickback (see the figure).
The equivalent circuit of the long trace lengths actually represents some parasitic inductance. If we account for the equivalent circuit above, then this actually looks like a different RLC model. So the goal here is to minimize this extra trace inductance “L” in the circuit to minimize the kickback ringing that could occur, possibly producing distortion and/or a different filter profile. This is just one example of how the amplifier, AAF, and ADC need to be tightly coupled together to make the signal chain work effectively.
There will always be reasons for having buffered and unbuffered architectures for high-speed ADCs. An unbuffered high-speed ADC can require a more complex analog interface design, but provides significant benefit to the overall system efficiency in terms of power. The unbuffered ADC design requires the analog interface design to be integral with the sampling network operation. This includes the amplifier, AAF, and ADC’s internal sample network. This task can be performed for most applications given the variables as described above are given careful consideration.
Analog-Digital Conversion: Seminar Series, Walk Kester, Walt Kester, Analog-Digital Conversion, Analog Devices, 2004, ISBN 0-916550-27-3; also available as The Data Conversion Handbook, Elsevier/Newnes, 2005, ISBN 0-7506-7841-0