Op-amp performance has advanced dramatically during recent years, but the relative advantages between bipolar input amplifiers and FET types remain the same. FET input parts are still characterized by superior bias current specifications, while bipolar devices retain the edge for better offset voltage tolerances. For example, no non-chopper FETs can match the 80 µV and 400 nV/°C numbers of the bipolar, single-supply LT1013A.
Unfortunately, the large 20-nA (typical) input bias requirement of the ’1013 (although already better than most single-supply bipolar op amps) makes it unsuitable for many applications, such as low-level integrate-and-hold circuits, for which it would otherwise be ideal. Moreover, standard bias current cancellation tricks, tremendously effective techniques that are integrated onchip in dual-supply amplifiers like the OP177 and LT1028, don’t work for positive-supply-only devices because the input networks of single-rail amplifiers need a bias current sink. It’s obviously impossible to sink current from an input pin that’s already referenced to the negative rail. Obviously.
At least I always thought this was impossible. But that was before I read Bob Pease’s column (“What’s All This R-C Filter Stuff, Anyhow?” Electronic Design, March 18, 1996, p. 123) in which he presented a bizarre circuit (Fig. 1) as an April 1st joke brain teaser. Amazingly, if the base-emitter junction of any ordinary silicon npn transistor is forced to zener and thereby sink a positive emitter current (Ie), a small negative collector current (Ic ≈ −Ie/10,000) will flow even if the collector is as much as a few tenths of a volt below ground! Good joke! The reader gets the definite impression, however, that Mr. Pease doesn’t think this circuit has much practical potential except for baffling and confusing poor unsuspecting analog EEs. But I think it’s perfect for making a tiny amount of negative current where no other negative voltage source exists.
This is exactly the function performed by Q1 and Q2 in Figure 2. A1 adjusts Q3’s base voltage until the drive to Q1’s emitter produces just enough negative collector current to balance the ≈ −20-nA bias current at A1 pin 2. By doing so, it produces a similar current at Q2’s collector and, therefore, A2 pin 6. If R4 is adjusted to compensate for asymmetry between the A1-Q1 and A2-Q2 pairs, A2’s bias can be nulled exactly to zero. Notice that the signal inversion provided by Q3 negates the inversion imposed by Q1 and Q2, where emitter-going-positive = collector-going-negative.
Changes in A1’s and A2’s bias currents due to temperature changes and aging can be expected to track well. And if Q1 and Q2 are closely coupled thermally, the nulling of A2’s bias current will be stable with time and temperature. This makes bias-nulled A2 a terrific candidate for inverting-amplifier applications where both voltage and current offset errors are of critical interest.
No fooling.