Solve The Issues Associated With Analog-To-Digital IP Integration

The huge increase in variety and number of ways people interact with electronic communications systems is no secret. More cell phones, wireless computers, and other multifunction, media-rich products such as PDAs, MP3 players, and digital cameras appear on the market every day. Analog circuitry is always needed to link this digital logic with the physical world. At its simplest, that means analog-to-digital-conversion (ADC) or digital-to-analog-conversion (DAC) chips are needed to convert analog signals to digital signals, or vice versa. At its most complex, it means a system on a chip (SoC) must combine virtually all of the analog and digital circuits that a device needs to function.

The level of resources and the diversity of expertise required for this kind of integration make it difficult for companies to develop these all-encompassing SoCs on their own, so many SoC makers seek turnkey pieces of circuit design or intellectual-property (IP) blocks developed by third parties. Of course, mixed-signal SoC integration challenges are numerous. But SoC-integrated analog IP is an absolute must in today's digital world, especially with the proliferation of portable devices.

SoC designers can overcome obstacles that often get in the way of integrating high-performance analog IP products into an SoC. Ways to do this include proper placement and routing, and dealing with substrate and noise-coupling issues. There are also laser fine-tuning techniques that can improve analog IP performance and accuracy.

Avoiding Interference Designers must take care to reduce undesired interference between different digital IP blocks and analog IP blocks, especially for cell phones and other portable devices where analog and power-consuming circuits co-exist. For example, placement of IP blocks within the SoC design affects how the IP itself behaves and how a block might affect other neighboring IP blocks. Interference between one IP block and another will have an impact on the performance of each, and thus the behavior of the SoC. Placing noisy IP circuits away from quiet and clean IP circuits is a good (and obvious) practice to follow. The SoC designer and the layout engineer must work together with awareness that different constraints govern each IP block.

Applying time-honored design placement and routing rules avoids interference. The first rule of thumb is to use the deep n-well layers available in most CMOS technologies to reduce coupling between NMOS transistors and the substrate. Another good rule is to systemically employ double-guard rings to isolate sensitive analog IP from the surrounding noisy circuits. One also has to be careful with placement, as noise can affect the accuracy of the analog IP, such as voltage references. Also, today's systems run at very high frequencies. That means the digital circuits switch at a very high rate, inducing lots of switching noise. The accuracy and performance of the analog IP is affected by this noise and therefore should not be placed near fast-switching digital IP, if possible.

Mechanical stress induced in the silicon substrate during the packaging process can also affect the accuracy of analog circuits. Suppose, for example, an SoC designer is integrating a low-dropout (LDO) voltage regulator into his or her design. The designer will need to account for the mechanical stress induced by the packaging process within the silicon crystal, which has an impact on the electrical characteristics of the LDO IP cells. Those mechanical constraints reach their maximum at the die's corners, so placing the LDO IP cells at these locations isn't recommended. Figure 1 shows the best regions for placement of the LDO IP cells in the typical floor-plan representation of a square die.

In general, placing the cell right in the middle of the die achieves higher accuracy. But another acceptable position would be along the longest edges of the chip. In addition, when used with high output current, LDO cells generate significant amounts of heat near VIN and VOUT of the cell I/Os. Therefore, VIN and VOUT I/Os should be positioned as far as possible from temperature-sensitive circuits.

For routing, it's always recommended to use separate power and ground lines for digital and analog circuits. Routing over sensitive IP blocks can induce mechanical stress that will affect the accuracy of the blocks. Therefore, it's not recommended to route over sensitive IP circuits. The connection between the output of the IP block and the load should have a very low parasitic resistance (large metal line) to optimize the load regulation that can affect output-voltage accuracy.

If the IP uses external components, such as capacitors, the placement of these components and the distance of these components from the IP have a direct impact on analog IP performance. The farther the capacitors are from the IP, the higher the parasitic resistance, which has a direct impact on the IP's regulation and output. The aforementioned LDO example can serve to illustrate the importance of placing the capacitors near the output, as shown in Figure 2.

Substrate Noise Coupling The relentless shrinking of semiconductor geometries has made substrate noise coupling a bigger issue for designers of new and more highly integrated SoCs. One can reduce coupling noise between sensitive analog circuits by employing state-of-the-art CMOS manufacturing processes: Features like triple wells and deep trenches help IC designers reduce coupling between circuit blocks. Either capacitive or inductive coupling between highly integrated designs with a shared substrate can induce coupling noise. The deep n-well, shown in Figure 3, will have a higher capacitance between the p and n regions, thus reducing the effects of coupling noise. Placing the n transistors in a deep n-well of noisy IP blocks will reduce noise to the rest of the SoC.

Another way to lower coupling noise, thyristor effect, and latchup is by introducing an isolation layer between transistors. The shallow-trench-isolation (STI) technique can introduce this isolation layer, and reduces the electrical crosstalk between adjacent transistors. This process happens at the manufacturing level, where the isolation is achieved by etching and deposition. Previously, growing a silicon oxide layer between transistors achieved isolation.

STI technology supplies the isolation required without the added mechanical stress on the device. One can use either the grown silicon-oxide layer method or the STI method to form an isolation layer between the transistors. However, for both methods, the layer that needs the isolation must be conceived and mapped during the layout process; the silicon substrate is masked to protect areas that don't require the oxide (isolation).

For the first method, a wet oxidation process is applied to the area of interest, which in turn grows a bubble of silicon dioxide that acts as an isolation layer between the transistors, as can be seen from the TEM image in Figure 4. Such a method is mostly used for processes of 0.35 microns or higher. For processes smaller than 0.35 microns (0.25 microns or lower), the transistors are placed closer together. This presents a challenge in creating the isolation bubble as done in the first method. The volume expansion, upon oxidation, creates a compressive stress that can cause dislocation defects in the substrate. Therefore, a channel is etched using reactive ion etching (RIE) between the transistors. Then, low-pressure chemical vapor deposition (LPCVD) and chemical-mechanical polishing (CMP) are used to complete the STI process. Electrical current traveling through the substrate will encounter the isolation and thus have to travel deeper into the substrate to go around it.

Power Issues Managing the output voltage stability over temperature variations is a very important factor in integrating high-performance analog IP into the SoC, especially for high-volume applications (e.g., cell phones) that must operate in harsh environments. A lower temperature coefficient means higher output-voltage stability.

Another major challenge for SoCs targeted at portable devices involves the power source. Most portable devices use lithium-ion batteries, which, when fully charged, supply 4.2 V. This presents a need for interfacing this voltage to the low-voltage transistors inside the SoC. Today's CMOS processes have two different oxide thicknesses, which allow for higher-voltage operation. However, these thicknesses permit up to 4.2 V or higher voltages. For example, a 0.18-micron process has both a thin oxide layer and a thick oxide layer that allows for 1.8- and 3.3-V operations, respectively.

Laser Fine-Tuning Laser fine-tuning technology that can fine-tune the resistance between two highly doped regions can also fine-tune the performance of a circuit that's limited by fabrication process variations. For example, LTRIM's FasTrim technology relies on accurately controlling the dopant concentration profile in standard diffused resistors using the heating effect of a focused laser beam. Figure 5 shows a lateral view of a device made of two heavily doped silicon regions (p+ or n+ standard diffusion) kept apart by a lightly doped channel (n-well or p-well standard diffusion).

Initially, the resistance between the two heavily doped regions is very high because the structure is equivalent to two opposite diodes. By focusing a laser beam on the channel, the laser beam heats and creates a melted silicon area that encompasses both the heavily doped regions and the lightly doped channel. Once the silicon reaches liquid phase, dopants in heavily doped regions start to diffuse faster (10,000 times faster) into the channel, which gradually reduces the resistance between the two heavily doped regions. We call this new device a laser-diffused resistor. By accurately controlling the physical parameters of the laser, one can accurately control the quantity and the profile of dopant concentrations in the channel. Consequently, it enables fine adjustments to the resistance of the laser-diffused resistor.

While the challenges appear daunting, one can achieve reliable, cost-efficient SoC designs that combine both digital and analog IP. Designers can use time-honored methods to integrate high-performance analog IP products into an SoC.