Squeeze 10-Bit Performance From An 8-Bit ADC, Part 3: Self-Dithering ADCs

July 2, 2008
Designers can construct a triangular additive dither that only requires two pulse-width modulators and an XOR gate. However, it may be possible to dither without any additional hardware at all.

Self-Dithering

If the input signal moves at least the analog-to-digital converter’s (ADC’s) resolution (Δ) over the time it takes to take multiple samples, the average result of these multiple signals will increase the resolution. However, this data-specific technique doesn’t work well for very slow-moving or dc values.

Noise

Noise is a random signal that has some peak-to-peak value and an average value of zero. As odd as it may sound, noise is a great dither and can make increasing your resolution easier. The peak-to-peak noise must be bigger than the Δ of your 8-bit, 2.048-V range ADC (see the figure).

Although the dither value was set for 20 mV p-p, the actual value over these particular 16 samples was 17 mV, and the average of all 16 values was 0.12 µV. This is the nature of a random signal such as noise. The more samples the better, as the signal acts like an ideal dither. For getting 2 bits of extra resolution, 16 samples are adequate. If your ADC has a high enough sample rate, increasing the number of samples to 32 improves performance.

Sometimes there is enough noise in your system to act as your dither. While generating this much noise could be difficult in an 8-bit ADC, the technique works very well for higher-resolution (more bits) ADCs.

Self-Dithering ADCs

The difference between the quantized and actual signals is always in the range of ±Δ. For a moving signal, the average is zero. The RMS value of this quantization error is (Equation 1).

The RMS error is proportional to the resolution. The maximum allowable sinusoidal signal has an RMS value of the range divided by the square root of eight. The signal-to-noise ratio (SNR) is (Equation 2).

So, an ideal ADC will have an SNR of 6n+2.

Now, like ideal op amps, ideal ADCs are a myth. Every ADC is going to have additional sources of noise, resulting in a small SNR. The source of all the noise is unknown to the user, but it can be summed up as an actual SNR. One method used to measure ADC noise assumes that all the noise was quantization error and then calculates the effective numbers (Equation 3).

A 16-bit ADC, then, should have 98 dB of SNR. If the actual SNR is 89, the ADC has 14.5 effective bits. Any time the SNRACTUAL is 6 dB less than SNRIDEAL, there is at least a bit of noise added from some source. If this is the case, the ADC is self-dithering and the signals can be averaged for increased resolution.

Any signal that you digitize is a combination of signal (S) and noise (N). Multiple signals are coherent and can be added together, while noise, being noncoherent, adds as the square root of the sum of the squared values. Equation 4 shows that adding multiple samples causes an increase in the SNR by the square root of the number of samples.

In effect, if you average four samples, you get an extra bit of resolution. Average 16 samples and you get 2 extra bits. This averaging is also known as decimation, as the data coming out has a reduced sample rate. Increasing the decimation by a factor of four (two octaves) causes an extra bit (6 db) of resolution. As a result, averaging increases resolution by 3 dB/octave.

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