Ian Beavers

Staff Engineer,
Analog Devices

Ian Beavers is an Applications Engineer for the High Speed Converters team at Analog Devices Inc., Greensboro, N.C. He has worked for the company since 1999. Ian has over 15 years of experience in the semiconductor industry. Ian has earned a bachelor's degree in electrical engineering from North Carolina State University and an MBA from the University of North Carolina at Greensboro. Ian is an EngineerZone expert in the High-Speed ADC Support Community. Feel free to send your questions to IanB at the Analog Devices EngineerZone Online Technical Support Community.

When 1 + 1 = +3 (dB): Averaging ADC Channels to Improve NSD 2
Averaging techniques can help engineers locate that last +3 dB of increased SNR and –3-dB reduction in NSD in DAQ systems using high-speed ADCs.
Noise Spectral Density: A “New” ADC Metric?
The most important high-speed analog-to-digital converter (ADC) performance metric has slowly changed over time, as has the measurement of ADC performance due to ever-increasing bandwidth requirements of signal acquisition systems.
Gigasample ADCs Promise Direct RF Conversion
As analog-to-digital converter (ADC) designs and architectures continue to advance using smaller geometry process nodes, a new class of gigahertz ADC products has begun to emerge.
Understanding Spurious-Free Dynamic Range In Wideband GSPS ADCs
For gigasample-per-second (GSPS) ADCs, one of the most important ac performance specifications is SFDR. It simply defines the capability of the ADC, and the system, to decipher a carrier signal from other noise or any other spurious frequency.
Demystifying Deterministic Latency Within JESD204B Converters
One of the key features of the JESD204B third-generation high-speed serial converter interface is its ability to establish a deterministic latency for each converter in the system. When this feature is understood and used correctly, it can create a synchronized or interleaved sampling system across many ADCs in a single system.
Prototyping Systems: JESD204B Converters And FPGAs
Prototyping the link of a JESD204B converter can be simplified by breaking down the steps into FPGA choice, firmware IP, modeling, simulating, validating the final performance, and finalizing the register configuration.
Pair The Right JESD204B Converter With Your FPGA
With more analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) now supporting the latest JESD204B serial interface standard, questions are arising about the best way to interface FPGAs to these analog counterparts.
Synchronize Multiple ADCs With JESD204B
System designers must overcome key challenges to achieve full timing closure for sampling synchronization such as printed-circuit board (PCB) layout considerations, matched clock and SYSREF generation to meet timing, SYSREF periodicity, and digital FIFO delays.
Slay Your System Dragons With JESD204B
The JESD204B serial data link interface was developed to support the growing bandwidth needs of higher-speed converters. It provides a higher maximum lane rate while supporting deterministic latency and harmonic frame clocking.
Kickstart Your System Designs With JESD204B 1
The new JESD204B interface can move large quantities of data easily for processing by taking advantage of higher-performance converters that are compatible and scalable with open-market FPGA solutions.
Deliver Quad-HD Video Over HDMI Cables
3Gbps HDMI interface solutions provide new features to the video space that were not previously available in past versions of the HDMI specification. However, system designers must be aware of 3Gbps signal constraints to maximize system performance.
Understanding the AirPods' Rise
Q&A: What’s New in the Wireless Audio Market? Interview with Jawad Haider, Marvell Semiconductor Read Now
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