Michael White

Michael White is the senior product marketing manager for Mentor Graphics’ Calibre Physical Verification products. Before joining Mentor Graphics, he held various product marketing, strategic marketing and program management roles for Applied Materials, Etec Systems and the Lockheed Skunk Works. Michael received a BS in System Engineering from Harvey Mudd College. He also holds a MBA/BS in engineering management from the University of Southern California.

Articles by Michael White
Silicon Photonics Bring New Capabilities To IC Design
Emerging silicon photonics technology holds a great deal of promise in computing and communications for sheer performance, reduced power, and overall increases in bandwidth.
16- And 14-nm Designs Await On 2014’s Horizon 1
2014 should be a very interesting year, with a breadth of activity across three technology nodes. 20 nm will move from the early-adopter crowd towards more mainstream production customers, while 16 nm/14 nm will see many test chips in preparation for its production ramp. 10 nm will take its first baby steps.
Qualification Is Just The Beginning
Press releases can make it seem like EDA tool qualification for a particular IC process node is the “end game.” But in truth, qualification is just the first publicly visible step of ongoing collaborations between an EDA vendor and the foundry.
Pattern Matching: The Next Step In EDA’s Evolution
Verification based on pattern matching not only makes it easier to express the design rules, but the whole physical verification definition process also gets simpler and moves faster.
It’s Time To Change To The OASIS Data Format 1
Using OASIS as your common exchange format will significantly reduce data volume. With less data to move around, your EDA tools will likely run faster, and tapeout to your foundry will be far easier than dumping a disk drive into a FedEx box.
Make The Leap From Test Chips To Production Designs At 20 nm
2012 was the year of test chips for the 20-nm technology node. Most leading fabless semiconductor companies spent 2012 preparing for their first production designs that will be taping out in 2013. As we start the transition from test chip evaluation to real production, it is perhaps a good time to reflect back on what we have learned about the IC design process for 20 nm.
Companies Ramp Up To Move From 20 nm To The Next Node In 2013

Well, 2012 has come to a close. It looks like all the Mayan “end is nigh” forecasts were good movie hype, but we’re all still here. In fact, fabless companies, foundries, and EDA suppliers have made real progress in preparing for future technology nodes. It’s time to reflect on the past year and what the world has in store for the future in 2013.

Letters From The Front Line At 28 And 20 nm
The 28-nm node is becoming mainstream, and early adopters are having their first go at 20 nm. Of course, there’s a lot more physical verification (PV) work and associated processing.
Separate The Hype From The Reality In 3D-ICs 2
Michael White takes a look at the current state of 3D IC chip packaging including 3D die-on-die stacking techniques and a variation called 2.5D die-on-silicon interposer packaging.
Know Your Mandatory And Recommended 20-nm Tapeout Requirements
The move to the 20-nm process node presents challenges for tapeout, but they're not insurmountable. Mentor Graphics' Michael White cuts through the EDA marketing hype and takes a pragmatic look at what 20 nm means in terms of tool flows and verification.
While 28 nm Is Still Teething, 20 nm Will Be A Barrel-o-Monkeys
Even as 28-nm production is ironed out, 20 nm is coming on, bringing with it double-patterning lithography and changes to design-rule checking and other verification parameters. Mentor Graphics' Michael White has the details in this column.
Does Double Patterning Mean The End Of The World?
Scanner resolution improvements have diminished since the 193-nm wavelength became commonplace. Today’s technologies are sufficient for 28-nm IC designs using immersion, but not beyond without additional assistance from the software solutions.
What Does Design Rule Signoff Really Mean—And When Should I Care?
Each time the semiconductor industry moves to a new technology node, everybody needs a new set of design rules to ensure IC manufacturability at these smaller dimensions using different processes and techniques.
Are We Ready For Physical Verification Standards?
Everyone is busy, so we’d all like to find a way to do less work and achieve the same results, right? Theoretically, creating one physical verification (PV) syntax standard that all design rule checking (DRC) tools could read would save the foundries a tremendous amount of effort and time when developing DRC decks for each new node.
What Does Signoff Verification Inside Implementation Really Mean?
Given the challenges cropping up at 45 nm and below, the industry must begin moving toward the use of signoff-quality DRC and design for manufacturing (DFM) engines inside all elements of their implementation flows. Michael White examines some of the requirements driving the need for full-featured signoff engines during design layout.

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