Michael White

Michael
White

Michael White is Director of Product Marketing for Mentor Graphics’ Calibre Physical Verification products. Before joining Mentor Graphics, he held various product marketing, strategic marketing and program management roles for Applied Materials, Etec Systems and the Lockheed Skunk Works. Michael received a BS in System Engineering from Harvey Mudd College. He also holds a MBA/BS in engineering management from the University of Southern California.

Articles
IoT, Cost-per-Transistor Extend Lifetimes of Established Technology Nodes
Continued demand for established nodes has extended their lifecycles, creating unexpected challenges in physical verification, design-for-manufacturing (DFM), and manufacturing.
Node Wars: A Look Back at 2014, and Different Roads for 2015
It’s a fun time of year to take stock of all that the electronics industry achieved in the past year, and to anticipate the interesting trends coming in 2015.
A Look Behind the Mask of Multi-Patterning
The commonality between 20/16/14 nm, 10 nm, and likely 7 nm is the need to use one form or another of multi-patterning (MP). This article explores the various MP approaches, how they differ by technology node, and where the IC manufacturing/IP/EDA ecosystems are in the delivery of solutions.
Get Ready To Hit 10 nm Out Of The Park
10 nm is in the midst of final process development tweaks, with early IP development now in full engagement across the early process node adopters and the ecosystems.
Silicon Photonics Bring New Capabilities To IC Design
Emerging silicon photonics technology holds a great deal of promise in computing and communications for sheer performance, reduced power, and overall increases in bandwidth.
16- And 14-nm Designs Await On 2014’s Horizon 1
2014 should be a very interesting year, with a breadth of activity across three technology nodes. 20 nm will move from the early-adopter crowd towards more mainstream production customers, while 16 nm/14 nm will see many test chips in preparation for its production ramp. 10 nm will take its first baby steps.
Qualification Is Just The Beginning
Press releases can make it seem like EDA tool qualification for a particular IC process node is the “end game.” But in truth, qualification is just the first publicly visible step of ongoing collaborations between an EDA vendor and the foundry.
Pattern Matching: The Next Step In EDA’s Evolution
Verification based on pattern matching not only makes it easier to express the design rules, but the whole physical verification definition process also gets simpler and moves faster.
It’s Time To Change To The OASIS Data Format
Using OASIS as your common exchange format will significantly reduce data volume. With less data to move around, your EDA tools will likely run faster, and tapeout to your foundry will be far easier than dumping a disk drive into a FedEx box.
Make The Leap From Test Chips To Production Designs At 20 nm
2012 was the year of test chips for the 20-nm technology node. Most leading fabless semiconductor companies spent 2012 preparing for their first production designs that will be taping out in 2013. As we start the transition from test chip evaluation to real production, it is perhaps a good time to reflect back on what we have learned about the IC design process for 20 nm.
Companies Ramp Up To Move From 20 nm To The Next Node In 2013

Well, 2012 has come to a close. It looks like all the Mayan “end is nigh” forecasts were good movie hype, but we’re all still here. In fact, fabless companies, foundries, and EDA suppliers have made real progress in preparing for future technology nodes. It’s time to reflect on the past year and what the world has in store for the future in 2013.

Letters From The Front Line At 28 And 20 nm
The 28-nm node is becoming mainstream, and early adopters are having their first go at 20 nm. Of course, there’s a lot more physical verification (PV) work and associated processing.
Separate The Hype From The Reality In 3D-ICs
Michael White takes a look at the current state of 3D IC chip packaging including 3D die-on-die stacking techniques and a variation called 2.5D die-on-silicon interposer packaging.
Know Your Mandatory And Recommended 20-nm Tapeout Requirements
The move to the 20-nm process node presents challenges for tapeout, but they're not insurmountable. Mentor Graphics' Michael White cuts through the EDA marketing hype and takes a pragmatic look at what 20 nm means in terms of tool flows and verification.
While 28 nm Is Still Teething, 20 nm Will Be A Barrel-o-Monkeys
Even as 28-nm production is ironed out, 20 nm is coming on, bringing with it double-patterning lithography and changes to design-rule checking and other verification parameters. Mentor Graphics' Michael White has the details in this column.
Commentaries and Blogs
Guest Blogs
May 29, 2015
blog

Engineering Education: Fact and Fiction 1

I have taken a keen interest in the dialogue (that has been going on for many years) about the quality of engineering education in the U.S....More
May 1, 2015
blog

Transition from the Academe to the Industry Unraveled (Part 2) 2

Some few months ago, I wrote an article contrasting academe and work life as well as the adjustments and precautions that had to be made by a typical fresh graduate......More
Mar 6, 2015
blog

Programming Efficiency: Part 2 2

A number of years ago I did some work on a PABX. The device was electromechanical and far from state of the art, but the owner had been talked into spending a bunch of money expanding it and couldn’t justify scrapping it....More

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