Reference flows pave the way to 3D IC Through-Transistor-Stacking
Three silicon-validated Reference Flows within the Open Innovation Platform that enable 16FinFET SoC designs and 3D chip stacking packages have been released by the Taiwan Semiconductor Manufacturing Company (TSMC). The Reference Flows are; TSMC’s 16FinFET Digital Reference Flow, the 16FinFET Custom Design Reference Flow, and the 3D IC Reference Flow.
So What's Good About Them?
For a start the 16FinFET Digital Reference Flow uses the ARM Cortex-A15 multicore processor as a validation vehicle for certification. What this does is help designers adopt the new technology by addressing FinFET structure related design issues associated with complex 3D Resistance Capacitance modeling and quantized device width.
But it doesn't stop there, the flow also provides methodologies for boosting power, performance and area in 16nm, including low-voltage operation analysis, high-resistance layer routing optimization for interconnect resistance minimization, Path-Based Analysis and Graph-Based Analysis correlation to improve timing closure in Automatic Place and Route.
What about the 16FinFET Custom Design Reference Flow? This enables custom design by addressing the ever-increasing complexity of 16FinFET process effects and provides methodologies for design compliance in 16nm manufacturing and reliability.
Last but by no means least the 3D IC Reference Flow can provide silicon scaling, power and performance benefits by integrating multiple components on a single device. In addition it addresses emerging integration challenges through 3D stacking. Key features include Through-Transistor-Stacking technology; Through Silicon Via /microbump and backside metal routing; TSV-to-TSV coupling extraction.