Newest Chips Are Stacking the Decks—With Memory

Stacking DRAM has been part of the high-bandwidth memory (HBM) systems found in high-end GPUs like AMD’s R9 Radeon and NVidia’s latest Tesla P100. HBM takes advantage of both 3D stacking and a wider, on-chip memory bus, greatly increasing bandwidth and capacity.

DRAM is not to be outdone, but it is trailing in stack size. Samsung’s latest 128-Gbyte DDR4 memory (see photo) uses a four-level stack. Many multilayer memory devices employ a bonded stack where each chip is wired to the base in the same fashion that a single die is wired. This requires that connectivity be done at the edge of the chips. Newer devices, including Samsung’s DRAM, employ through-silicon vias (TSVs). This is comparable to through-holes in a printed circuit board (PCB). It has multiple advantages, including the ability to place holes almost anywhere on the die. Samsung’s roadmap has eight- and 16-layer devices on it.

The number of layers varies with each type of device because there are other issues than just 3D stack connectivity involved in the design process. For example, DRAM operates at faster speeds than flash memory.

Still, there are more advantages driving the migration to higher stacks, including power savings and increased bandwidth. The trend toward massive in-memory databases is pushing capacities on the server side, while more compact platforms are pushing the technology in the embedded space.

There may be a limit to the number of layers that are practical, but for now we have not reached that limit.