Introduction
You’ve just spent a large sum of money for that new stereo and it’s time to fine tune your listening environment with the graphic equalizer. But wait. How can you do that objectively? Hearing can be a subjective experience and very much dependent on the individual. What is needed is an objective analysis of the sound. The Audio Analyzer described in this article performs an error-free optimization of a stereo output from 20Hz to 20Khz.

Functional Description
The Audio Analyzer is composed of two primary functional blocks: the White Noise generator and the Spectral Analyzer. The white noise is fed into the left and right stereo inputs. The amplified noise from the speakers is then picked up by an on-board electret condenser microphone, which provides the signal to the Spectral Analyzer. The Spectral Analyzer measures the signal at 8 unique frequency bands in the audio spectrum and displays the results in a bar graph format. The Spectral Analyzer, White Noise Generator, and display decoder/driver were all implemented from a single Cypress Microsystems CY8C26443 PSoC chip

To use the instrument, the user runs a stereo patch cable between the RCA jacks on the side of the unit to an appropriate input on the rear of the amplifier under test. The stereo should then be turned on and the input selected. While standing in the desired listening location, turn the instrument on, and select the right channel. White noise should be heard from the speaker. The user should then adjust the equalizer settings on the amplifier until a flat response is observed on the display of the analyzer. This procedure is repeated for the left channel

Hardware Description
The schematic for the Audio Analyzer can be seen in Appendix A. The microphone is biased and fed into port P01. The amplified microphone signal is then output at P03 which is fed directly into P06 via a 100K resistor and to P04 through a 2Khz low pass filter.

The analog white noise signal is output at P02. This signal is mechanically switched by the user between two 20Khz low pass filters that feed RCA jacks for the right and left channels.

Two LiteON LED arrays are used to provide a multiplexed 8X8 bar graph display (two of the columns are not used). Port P2 is used to directly drive the rows while port P1 drives Q1 through Q8 for the column drive.

The power supply consists of a Linear Technology LT1300 switch-mode regulator which is used to boost two AA batteries to 5 volts.

All of the functionality for the Audio Analyzer takes place in the PSoC device. Figure 2 illustrates each of the blocks used within the chip for the analyzer.

A breakdown of the block usage is:

  • White Noise Generator: DBA03, DCA04, DCA05, DCA06, DCA07, and ASB13
  • Microphone Amplification: ACA00, and ACA01
  • Programmable Bandpass Filter: ASA10, ASA21, ASB11, ASB20, DBA00, and DBA01
  • A/D Conversion: DBA02, ACA02, ACA03, and ASA12
  • General Purpose Timing: DCA06

The following sections provide a detailed description of the PSoC design:

White Noise Generator
As seen in Figure 3 , the white noise generator was built from two of the functional blocks within the PSoC chip. The first block is a 24-bit Pseudo Random Sequence generator which is clocked at 40Khz. Each clock also generates an interrupt where the lower six bits of data from the PRS is transferred to the second block, a 6-bit DAC. Since a 24-bit PRS can produce a total of 224-1 unique numbers before repeating, the sequence will run for (224-1)/40000 seconds or about seven minutes before repeating.

The noise generated by this system is not true gaussian white noise (GWN) because the amplitude of the signal is uniformly distributed within a finite range of 0 to 5 volts and the bandwidth is limited to 20Khz. In fact, if you look at the signal with an oscilloscope set to high sweep rate, you would see a waveform that looks like Figure 4 <data>08D0C9EA79F9BACE118C8200AA004BA90B02000000080000000C0000005F0052006500660038003000320031003000360032000000</data> .

If the sweep rate is reduced however, the signal on the oscilloscope will look like Figure 5 <data>08D0C9EA79F9BACE118C8200AA004BA90B02000000080000000C0000005F0052006500660038003000320031003200310035000000</data> , which looks (and sounds) a lot like white noise.

Figure 6 shows a 4096 point FFT of the generated noise signal. Here, we can see that spectrally, our synthetic noise does look like GWN out to 20Khz.

Spectral Analyzer
Figure 7 shows the block diagram of the spectral analyzer circuit. The items outlined in black are hardware functions implemented within the PSoC chip while those in blue are outside the chip. Red functional blocks are implemented in software.

The process begins with the white noise for the system under test being detected by the microphone which is amplified by the MIC AMP (Block ACA00). This amplifier provides a gain of 16 and acts as a buffer. The amplified microphone signal is then routed outside the chip to port P03. This signal is then connected directly to input port P06 and to the input of a 2Khz low pass filter. The output of the LPF is fed into port P04. Pot inputs P04 and P06 are muxed into the Intermediate amplifier.

The 2Khz low pass filter is used for the lower four band pass filter combinations. The reason for this is because the two lowest frequency band pass filter configurations (110 and 220Hz) sample at 11788 and 23715Hz respectively. This translates into Nyquist frequencies of 5894 and 11858Hz. Using a 2Kz low pass filter blocks error causing high frequency signals from reaching the BPF for these lower frequencies. Although not needed for the 440Hz and 880Hz filters, the filter is left in place to simplify programming.

The Intermediate Amp adds an additional gain of two and passes the signal on to the programmable bandpass filter. The BPF is a fourth order Butterworth design based on the values derived by the BPF4_design spreadsheet provided by Cypress Micro. Each of the eight filter combinations has a gain of 0dB and a Q of 1.414. The characteristics for each filter can be found in Table 1

fc

fu

fl

BW

Q

113

160

80

80

1.414

226

320

160

160

1.414

453

640

320

320

1.414

905

1280

640

640

1.414

1,810

2560

1280

1280

1.414

3,620

5120

2560

2560

1.414

7,241

10240

5120

5120

1.414

14,482

20480

10240

10240

1.414

Table 1 - Bandpass Filter Characteristics

Figure 8 shows the frequency response of each of the eight filters overlapped on the same graph. Specific clocking and C-value information can be found in Appendix B. Except for the 15Khz filter, the C values are identical for each combination – only the clock is changed. To avoid overclocking, the C values had to be changed for the 15Khz filter. That is why its response peaks slightly higher than the other filters.

The software switches sequentially between the filter configurations giving each one a specific period to settle and a specific sample period. The lower frequency filters need more time to settle and a longer sampling period than the high frequency filters.

Following the filters is the EQU AMP (ACA02) or equalization amp. This amplifier provides a unique gain for each filter combination so that flat frequency response will be observed for an ideal system. Not shown is an additional gain boost amplifier in block ACA03.

The band pass filtered, analog signal is then fed into the DELSIG8 A/D. This device is clocked at 8Mhz to provide a sample rate of 31.25Kz. Although this sample rate is below the Nyquist rate for signals greater than 15Khz, it is acceptable in our application since we are not using the samples as a representation of the waveform.

As the A/D values become available, a software peak detector is employed to save the sample with the greatest absolute value during the period for each filter. At the conclusion of the filter period, the high value is saved in an eight-register circular buffer. The average of the eight previous readings is then calculated and saved. The upper three bits of this value are used as an index into a lookup table that contains the bar-graph patterns for the 8X8 LED display. An array of eight bytes is used to store the pattern for each spectral band.

The display driver is an interrupt service routine that occurs 800 times per second. During each pass of the routine, a single column of the display is driven. With 8 columns and an update rate of 800 columns per second, the entire display is updated 100 times per second.

External transistors are used as column drivers while individual port pins drive the rows. The circuit depends on the maximum current of 25mA for the port pins to control the drive to the row LEDs.

Code Description
The code has two fundamental modules: the main loop and the 40Khz Timer Tick. These modules are described in more detail below.

Main Loop
The pseudo code for the main loop is:

Main:
 

Initialize and start PRS
Initialize and start clocks
Initialize Variables
Start DAC
Start Amplifiers
Start DELSIG8
Set MIC AMP input to AGND
Set Autozero flag

         
Loop:        
  If BPF period is complete
   

Save current peak value
Average eight previous peaks
Select bar graph symbol
Load new values for next BPF
If Autozero AND all offsets are measured

     

Save Offset Values
Clear Autozero Flag
Set MIC AMP to P01

   

Set peak value to zero

  If A/D reading available
    If Filter has settled
     

Subtract offset from sample value
Perform absolute value if negative
If new value is > than last peak

        Save new peak

Timer Tick
The Pseudo code for the Timer Tick which occurs 40000 times per second is:

Get lower six bits of 16-bit PRS
Write six bit value to DAC6
Decrement BPF_Counter
If BPF_Counter =0
  Load BPF_Counter with Count Value (4)
         
  Decrement BPF_Timer
         
  If BPF_Timer =0
    Load parameters for next filter
     
    If Filter 0-3
      Set Mux to 2Khz Filter
         
    Else
      Set Mux to no Filter
         
   

Increment Filter Index
Load BPF_Timer with Filter-Specific Value
Load Settling_Timer with Filter-Specific Value
Clear SAMPLE flag

         
  Else
    If SAMPLE=FALSE
     

Decrement Settling_Timer
If Settling Timer = 0
Set SAMPLE flag

         
Decrement Disp_Timer
         
If Disp_Timer = 0
 

Load Disp_Timer with Count Value (50)
Drive next column in display with bargraph pattern

Note that the Timer Tick occurs at 40Khz, the BPF event occurs at 10Khz, and the Display Event occurs at 800Hz. Since the display has eight columns, the refresh rate is 100Hz.

Appendix B - Bandpass Filter Parameters

Bandpass Filter Parameter

LC Stage

fc

C1

C2

C3

C4

n

fs

fn

110

1

1

2

11

509

11788

5894

220

1

1

2

11

253

23715

11858

440

1

1

2

11

127

47244

23622

880

1

1

2

11

63

95238

47619

1760

1

1

2

11

32

187500

93750

3520

1

1

2

11

16

375000

187500

7040

1

1

2

11

8

750000

375000

14080

2

2

4

11

8

750000

375000

 

HC Stage

fc

C1

C2

C3

C4

n

fs

fn

110

2

2

3

13

509

11788

5894

220

2

2

3

13

253

23715

11858

440

2

2

3

13

127

47244

23622

880

2

2

3

13

63

95238

47619

1760

2

2

3

13

32

187500

93750

3520

2

2

3

13

16

375000

187500

7040

2

2

3

13

8

750000

375000

14080

4

4

6

13

8

750000

375000