The third generation of the dual-data-rate memory standard is gaining acceptance; here's a test suite that can smooth the way to compliance with the standard.
The transition to the third generation of the dual-data-rate memory standard (DDR3) is well underway. Most applications of the DDR3 architecture are trickling down from the computer market into embedded systems, mobile devices, and consumer electronics. For many applications, DDR3 offers a great balance between performance and power consumption.
Of course, migration to a new memory architecture isn’t without its challenges, particularly when it comes to embedded or portable applications. In the embedded scenario, DDR3 bus widths are different than they would be on a motherboard. Mechanical constraints come into play as well, making signal accessibility for testing an issue.
When it gets down to the nitty-gritty details of design and integration, there are even more issues to consider. One class of issues comes under the heading of interoperability. The DDR3 specification is a fairly thick protocol stack, with some elements of that stack being vendor-dependent. That means there will inevitably be interoperability issues between the memory devices themselves and the memory controller.
Yet another class of challenges is performance optimization. Designers may find that early prototypes don’t work at 100% efficiency and may not work at all. They might be using very fast memory and not get the expected throughput. Some of these problems can be sorted through by observing eye diagrams of bus transactions. But to do that, one needs tools that understand that the eye for a write may not be the same as one for a read.
To specifically address all of the needs relative to DDR3 design and integration, Agilent is offering a comprehensive DDR3 protocol test package that will span probes and slot interposers, a high-speed logic analysis module, and compliance and analysis software tools.
At the center of the offering is the 16962A logic analysis module, billed as the industry’s fastest with support for state speeds up to 2 Gtransfers/second. Timing speed is specified as up to 8 GHz (quarter channel; up to 400 Msamples deep). The module also sports a trigger sequence rate of 2 GHz, enabling it to capture events at full speed. A burst-recognizer trigger function is also included.
A logic-analysis module with those specifications is of little value unless you can physically access the DDR’s I/Os. To that end, Agilent has come up with a system for DDR ball-grid array (BGA) probing specifically for embedded applications. The probe eliminates the need for redesign or even any upfront planning for probing. There’s no longer any need to waste board space for a probe footprint. The probe, which attaches directly to the balls of the BGA, includes embedded resistors for isolation. It can be used for both physical and protocol measurements.
Also available is a slot interposer that enables quick and easy access to DDR3 memories with transfer rates of up to 1.6 Gtransfers/s. Additionally, the slot interposer enables simultaneous read and write captures when paired with the 169662A logic analysis module.
Once all of this data has been captured, there must be tools for analysis. Agilent is rolling out a comprehensive analysis environment to go along with the instrumentation and probe hardware. First is a protocol compliance tool, which performs quick and easy timing and protocol-violation checking. It will determine whether a trace complies with the JEDEC DDR3 spec, and it can also perform state testing. Results of the testing are provided in HTML format.
A second analysis tool, the performance tool, provides information on memory bus transactions that can then be used to optimize system performance. How does the existing bus implementation perform? How many cycles are being spent in reads, writes, or an idle state? The tool builds a histogram view of address access counts, telling the designers how many times the memory controller accesses individual memory addresses.
Last is an easy trigger tool that spares designers from the task of having to manually build triggers. Triggers are easily configured with automated logical-to-physical address translations.
The 16962A logic analysis module costs $38,135. A two-slot mainframe with touchscreen in which to house it costs $14,000. BGA probing systems start at $700 while the N4835A DDR3 slot interposer is priced at $40,800. The B4622A protocol compliance and analysis software package sells for $5500.