Evaluate Power-Supply Noise Rejection In Low-Jitter PLL Clock Generators

Clock generators that integrate phase-locked loops (PLLs) find many homes in network equipment. Their main function is either to generate high-precision and low-jitter reference clocks, or maintain a synchronized network operation. Most clock oscillators provide their jitter or phase-noise specification using an ideal, clean power supply. In a practical system environment, the power supply can suffer from interference due to on-board switching supplies or noisy digital ASICs. To achieve the best performance in a system design, it’s important to understand the effects of such interference.

PSNR Characteristics of PLL Clock Generators
Figure 1 shows a typical PLL clock generator. Since the output driver can have very different power-supply noise rejection (PSNR) performance for different types of logic interfaces, the following analysis will focus on the supply noise impact to the PLL itself.

Figure 2 shows the PLL phase model assuming that the power-supply noise V_N is injected into the PLL/VCO, and the divide ratios M and N are set to 1 (Fig. 2).

The PLL closed-loop transfer function from V_N(s) to φ_O(s) is given by

For a typical second-order PLL,

Equation 3 demonstrates that, in a PLL clock generator, the power-supply noise is rejected by 20 dB/s when the supply interference frequency is greater than the PLL 3-dB bandwidth. For power-supply interference frequencies between Ω_Z and Ω_3dB, the output clock phase varies with the power-supply interference amplitude as:

As an example, Figure 3 shows the PSNR characteristics of a PLL for two different settings of the PLL’s 3-dB bandwidth.

Conversion of Power Spectrum Spurs to DJ
When a single-tone sinusoidal signal, f_M, is applied to the power supply of a PLL, it produces a narrow-band phase modulation at the clock output, which can be generally described using Fourier series representation:

Here, n = 0 represents the carrier itself. When n = ±1, the phase-modulated signal is given by:

Equation 8 demonstrates that, when measuring the double sideband power spectrum S_V(f), if varible x represents the level difference between the carrier at f_O and the fundamental sideband tone at f_m, then:

where x = decibels relative to the carrier (dBc).

Since β is the maximum phase deviation in radians, the peak-to-peak deterministic jitter (DJ) caused by this small index phase modulation can be derived:

where DJ = picoseconds peak-to-peak (ps p-p).

The above analysis assumes that no amplitude modulation is contributing to the tone at f_M. In reality, both amplitude and phase modulation can be generated, reducing the accuracy of this approach.

Conversion of Phase Noise Spectrum Spurs to DJ
To avoid the amplitude-modulation effect when measuring the power spectrum S_V(f), one can instead calculate the DJ by measuring the spur in the phase-noise spectrum while applying a single-tone sinusoidal interference on the supply. With the variable y representing the measured single-sideband-phase spurious power at frequency offset f_m, the resultant phase deviation Δφ can be derived:

where y = dBc, Δφ = radians rms (rad_rms) in Equation 11, and Δφ = ps p-p in Equation 12.

It should be noted that the single-sideband phase spectrum in the above analysis isn’t the folded version of the double-sideband spectrum. That’s the reason for the 3-dB component in Equation 10. Figure 4 shows the relationship between the deterministic jitter and the phase spurious power given by Equation 12.

PSNR Measurement Techniques
This next section demonstrates five different ways of measuring the PSNR of a clock source, using the MAX3624 low-jitter clock generator as an example. The measurement setup in Figure 5 uses a function generator to inject a sinusoidal signal onto the power supply of the MAX3624 evaluation board. The amplitude of the single-tone interference is measured directly at the V_CC pin close to the IC. A limiting amplifier, MAX3272, is used to remove amplitude modulation, followed by a balun that converts the differential output into a single-ended signal for driving the different test equipment. To compare the results from different tests, all of the measurements were done under the following conditions:

• Clock output frequency: f_o = 125 MHz
• Sinusoidal modulation frequency: f_m = 100 kHz
• Sinusoidal signal amplitude: 80 mV_P-P

Method 1—Power spectrum measurement: When observed on a power spectrum analyzer, the narrow-band phase modulation appears as two sidebands around the carrier. Figure 6 shows the case when viewed using the spectrum monitor function of the Agilent E5052. The measured first sideband amplitude relative to carrier amplitude is -53.1 dBc, which translates to 11.2 ps_p-p deterministic jitter according to Equation 9.

Method 2—Single-sideband (SSB) phase spurious measurement: On a phase-noise analyzer, the power-supply interference will manifest itself as a phase spur relative to the carrier. The measured phase noise spectrum is plotted in Figure 7. The phase spurious power at 100 kHz is -53.9 dBc, which translates to 10.2-ps_p-p deterministic jitter using Equation 12.

Method 3—Phase demodulation measurement:Utilizing the Agilent E5052 signal analyzer, the phase-demodulated sinusoidal signal at 100 kHz is measured directly (Fig. 8), which gives the maximum phase deviation from its ideal position. The peak-to-peak phase deviation is 0.47°, which translates to 10.5 ps p-p at an output frequency of 125 MHz.

Method 4—Real-time scope measurement: In a time-domain measurement, the deterministic jitter caused by power-supply interference can be obtained by measuring the time interval error (TIE) histogram. On a real-time scope, the clock output TIE distribution will appear as a sinusoidal probability density function (p.d.f.) when a single-tone interference is injected into the PLL. The deterministic jitter can be estimated using the dual-Dirac model1 by measuring the peak distance between the mean of two Gaussian distributions from the TIE histogram.

Figure 9 shows the measured TIE histogram using Agilent’s Infiniium DSO81304A 40-Gsample/s real-time scope. The measured peak separation is 9.4 ps under the test condition mentioned above.

It should be noted that the memory depth of the real-time scope may limit the low sinusoidal modulation frequency that can be applied to the PLL supply. For example, if the test equipment has a memory depth of 2 Msamples/s when the sample rate is set to 40 Gsamples/s, that would only allow capture of jitter frequency components down to 20 kHz.

Method 5—Sampling scope measurement: When a sampling scope is used, a synchronous trigger signal is required for analyzing the clock jitter under test. Two triggering methods can be used for TIE measurements.

The first solution is to apply a low-jitter reference clock to the input of the PLL clock generator, and use the same clock source as the trigger for the sampling scope. Fig. 10 shows the measured TIE histogram, which gives a peak spacing of 9.2 ps. The advantage of triggering with a reference clock is that the measured TIE histogram peak separation is independent of the horizontal time delay from the trigger position. However, the measured TIE histogram might be affected by the triggering clock jitter. Therefore, it’s important to use a clock source with much lower jitter than the clock generator device under test.

Self-triggering is an alternate approach to eliminating the impact of triggering clock jitter. In this case, the output of the clock generator under test is separated into two identical signals using a power splitter. One signal is applied to the data input of the sampling scope, another one to the trigger input. Because the triggering signal contains the same deterministic jitter as the test signal, the histogram peak separation varies when the horizontal position of the scope main time base is swept through one period of the sinusoidal modulation frequency.

At a horizontal position of one-half period of the modulation signal, the peak separation on the TIE histogram will be twice the deterministic jitter from the test signal. Figure 11 shows the measured MAX3624 TIE histogram when the horizontal time delay is set to 5 µs. The estimated TIE peak separation is 19 ps, which gives an equivalent deterministic jitter of 9.5 ps p-p.

Figure 12 shows the measured TIE histogram peak spacing at a different horizontal time delay from the trigger point. For comparison, the TIE result is also shown when the sampling scope is triggered by a reference clock input.

Measurement Summary
The table summarizes the measured deterministic jitter at the MAX3624 125-MHz clock output, using the different methods that were discussed. It should be noted that measured DJ using a dual-Dirac approximation from the TIE histogram is slightly smaller than the DJ obtained from the frequency-domain spectral analysis. This is caused by the process of convolution of the sinusoidal jitter (SJ) p.d.f. with the Gaussian distribution of the random jitter component.¹ Therefore, the deterministic jitter extracted from the dual-Dirac model is only an estimation and should only be applied when the standard deviation of the random jitter is much smaller than the distance between the two peak separations of the jitter histogram.

For the relatively large interference used in the examples, the results were well correlated. However, when the level of interference drops relative to the random jitter, the time domain methods become less accurate. Furthermore, if the clock signal is corrupted by amplitude modulation, measurements using a power spectrum analyzer become unreliable. Therefore, of all the methods presented, the phase spur power measurement using a phase noise analyzer is the most accurate and convenient way to characterize the PSNR of a clock generator. The same method can be extended for evaluating the deterministic jitter aspect caused by other spurious products appearing on the phase noise spectrum.

Reference:
1. Agilent white paper, “Jitter Analysis: the dual-Dirac Model, RJ/DJ, and Q-Scale.”