Moving from external nonvolatile memory (NVM) to an internal embedded approach provides many benefits in system-on-a-chip (SoC) design: increased design accuracy, lower board costs, decreased board complexity, greater testability, better reliability, and increased security. If designers can also partition their designs so that they're realized in a logic CMOS process, the design will gain additional benefits, including lower power consumption and lower chip cost.
The process of integrating any intellectual property (IP), however, can be fraught with risk. But the good news is that the wise engineer can avoid the pitfalls by observing a few basic rules. The following checklist will help you keep your project on track as you move through its various phases.
PLANNING PHASE
- Thoroughly understand your NVM requirements. Only then can you begin to evaluate the capabilities, tradeoffs, and overall suitability of the various technologies for your design, ultimately enabling the best IP vendor selection.
- Verify the process compatibility details. High-performance NVM blocks are generally developed and qualified for a specific process node. If the process requirements aren't 100% compatible, contact the NVM IP supplier to help assess the risks, tradeoffs, and possible changes associated with the targeted fab.
- Verify the quality of the NVM block. Production-proven NVM IP will go a long way in mitigating integration risk. The NVM's robustness, testability, and general level of maturity must be weighed in the context of the overall design goals and risk management.
DESIGN PHASE
- Read the documentation! The majority of IP integration problems can be avoided by simply consulting the NVM block datasheets and release notes.
- Use the NVM supplier's simulation tools. The reputable NVM supplier will provide Verilog models and testbenches along with the NVM block. Using those tools should enable complete validation of both functionality and timing requirements within your design.
- Plan for test access. Even in well-partitioned designs, increasing levels of integration challenge access to internal circuit nodes. Therefore, it's critical that the NVM block supports testability and allows designers to take full advantage of special test modes possibly included in the NVM block.
- Obey the NVM block's layout restrictions. Many blocks have "keep-out" areas over which no high-speed or high-noise signals should be routed. The NVM may also have specific orientation requirements, where rotation in the layout may actually degrade performance.
- Confirm the design-rule-checking (DRC) and layout-versus-schematic (LVS) checks. GDSII layer mapping must match that of the SoC, but note that many NVM blocks violate the standard foundry design rules. As such, the NVM supplier should supply custom DRC and LVS decks or a list of expected errors to the standard foundry decks.
- Observe the metal coverage rules. Not only must the NVM meet the required metal coverage rules, the SoC must also incorporate sufficient fill metal around the NVM block to ensure that metal coverage is met in all regions of the chip layout.
- Make sure the NVM's voltage requirements are met. The NVM's specified voltage requirements are those at its input(s). Voltage droop between the SoC power pin and the internal NVM VDD can cause the voltage at the NVM block to be out of spec. Power-sequencing requirements may also come into play.
PRODUCTION PHASE
• An SoC that incorporates embedded NVM must be treated as a memory IC during the testing process. This typically includes a memory retention bake. Consult with the IP vendor to determine what additional testing is recommended for the NVM.
To learn more about embedded nonvolatile memory (NVM), attend the Logic NVM 2007 "Inside Tomorrow's Consumer Electronics" event on June 14 in Santa Clara, Calif. Experts will discuss the advantages and integration challenges of embedded logic NVM in consumer electronics, power management, radio frequency, and digital rights management. For more information, visit www.logicnvmevent.com.