Power semiconductors bring huge advantages to the design drawing board. They provide a faster and more reliable solid-state alternative for conventional mechanical parts. They also act as the enabling technology for completely new applications.

All told, power semis have become an increasingly critical element in the systems, equipment, and devices used in the workplace at home (and in the journey between the two). When it comes to selecting silicon devices for these systems, engineers the world over face the same challenges: How do they optimise efficiency, drive down component count, minimise noise, and reduce board space—without incurring performance or cost penalties?

Tradeoffs

The good news is that semiconductor manufacturers help engineers overcome these hurdles through new fabrication processes and techniques. Naturally, thanks to a combination of environmental concerns, legislation, spiraling fuels costs, and worries about security of energy supply, improving efficiency often tops the list of areas for improvement. However, two factors are making it harder to achieve ongoing efficiency improvements. 

First, with many power semiconductors already operating in the 95%+ efficiency range, achieving even a fraction of a percentage point improvement is much more difficult than, say, moving from 80% to 90% efficiency. Second, there’s the issue of tradeoffs, as illustrated by the impact of reducing on-resistance.

One method often employed by semiconductor manufacturers is to lower RDS(ON), which reduces losses and improves the efficiency of semiconductor devices such as MOSFETs. Another involves superjunction (SJ) technology using a deep trench process.

Toshiba, for instance, takes the latter approach with the company’s DTMOS technology, which is now on its fourth generation (Fig. 1). Power MOSFETs based on DTMOS-IV technology make ideal switching devices in switch-mode power supplies, lighting ballasts, and other power-supply applications that demand a combination of high-speed operation, high-efficiency, and low EMI noise.


1. The DTMOS-IV process, based on superjunction technology, can improve efficiency while reducing package size for power MOSFETs.

Because SJ MOSFETs offer ultra-low on-resistance below the silicon limit, they make it possible to shrink devices and save printed-circuit board space without power loss penalties. As a result, when deploying processes such as DTMOS-IV in high-speed, high-efficiency 600V power MOSFETs, they can offer up to 40% lower on-resistance than first-generation DTMOS products for the same die size.

DTMOS-IV also minimises MOSFET output capacitance (COSS) for optimised SPS operation at light load. Furthermore, a lower gate-drive capacitance (CGD) delivers improved dv/dt switching control, while an optimised RDS(ON)* QG figure of merit supports high-efficiency switching. Finally, by supporting lower dv/dt ratings, DTMOS-IV also reduces the tendency to ringing in high-speed switching circuitry.

Processes for Integration

Processes such as DTMOS-IV can significantly reduce package size and, thus, reduce board space while improving efficiency without incurring performance penalties. However, in other applications, processes that support very high levels of integration of different types of technology in the same IC can save board space by dramatically cutting component count.

Take, for example, a BLDC motor that needs to be driven by a 500V PWM sinusoidal output controlled by a host processor or a dedicated motor controller. This setup requires certain key circuit elements: a logic circuit, high- and low-side drivers, a three-phase power output stage, and a shunt resistor circuit for current sensing. It also requires various types of circuit protection, not to mention fast recovery (bootstrap) diodes. Minimising the component count needed to implement these various elements is crucial, which is why semiconductors based on silicon-on-insulator (SOI) processes are gaining more traction.

SOI using a trench isolation structure overcomes the barriers to integrating high-voltage switching structures, such as IGBT output stages and digital control circuitry, on the same substrate. Circuit elements are isolated using a thin layer of silicon dioxide (Fig. 2). This allows for an ultra-thin trench structure, enabling the dense fabrication of the active circuit elements. An example of SOI deployment can be found in a new series of highly integrated, single-chip inverter intelligent power devices (IPDs) launched by Toshiba at this week’s PCIM event in Nuremberg.


2. Silicon-on-insulator technology overcomes the barriers to integrating high-voltage switching structures, such as IGBT output stages and digital control circuitry, on the same substrate.

By reducing power loss by 20% compared to previous device generations, the TPD4144K and TPD4144AK IPDs offer single-chip, DIP26-packaged solutions to high-voltage PWM control for a number of applications, such as low-power fans and pumps and industrial automation systems. Each package integrates full three-phase inverter bridge operation, including input logic, a level-shift high-side driver, a low-side driver, a three-phase bridge output using optimised IGBT technology to provide current to the motor stator, and a three-shunt resistor circuit for current sensing.

Component count, board space, and cost are further reduced thanks to integrated fast recovery bootstrap diodes and on-board features such as undervoltage protection, thermal shutdown, and overcurrent protection, as well as a built-in 7V (typical) regulator. The end result is a single-chip device that only needs a logic input from a host microprocessor or motor controller to deliver effective motor control.