With verification still eating up most of the costs in the design cycle for complex systems-on-a-chip (SoCs), it behooves designers to seek out methodologies that can help them reduce the time and cost of verification. Meanwhile, tightening budgets dictate that designers focus on differentiating their end products. Much of that differentiation comes in the form of software, which represents a high return on investment compared with the hardware aspects of the system, which, for many systems houses, is increasingly embodied in a platform approach.
Even as the number of ASIC design starts is falling, the complexity of those ASICs is on the rise. Thus, the requirements for system validation and embedded software development are greater than ever. Designers know that external interfaces are a key aspect of the task, but they can’t stop there. Debugging methodologies need to be fleshed out and not approached in an ad-hoc fashion.
So on the heels of its acquisitions of HARDI Electronics and Synplicity, Synopsys has forged a rapid-prototyping flow that patches the holes in the ad-hoc debugging methodologies that have been cobbled together across the industry. Dubbed Confirma, the platform includes implementation and debug software; high-performance prototyping boards and systems; a transaction-based co-verification methodology; and intellectual-property (IP) and services offerings.
On the hardware side, the Confirma platform has three main elements. First, the CHIPit line of rapid prototyping systems comprises fully encased systems with a programmable interconnect architecture and capabilities for transaction-based co-verification. From HARDI comes the HAPS line of rapid prototyping boards, a better option for situations in which numerous software developers need the hardware for verification purposes. Rounding out the hardware line is the HapsTrak line of interface and expansion boards for the HAPS boards and CHIPit systems.
The software side of the equation runs the gamut of tools required for rapid prototyping. It starts with CHIPit Manager Pro and Certify for project management and partitioning of a hardware design into multiple FPGAs. Synplify Premier handles FPGA synthesis.
Within the CHIPit platform are all the emulation-like features that a virtual platform requires. Users can incorporate legacy RTL to reduce their modeling effort. A hardware adaptation layer connects the CHIPit hardware platform to the user’s workstation, on top of which is an application layer that enables designers to reuse and accelerate an existing simulation environment by moving the device under test into the CHIPit box. Finally, an SCE-MI interface connects the hardware with higher-level models running the application software.
Debugging of prototypes is made easier within the Confirma platform by the Identify Pro software for RTL debug. Identify Pro monitors simulation runs to ferret out error conditions. It can also be set to trigger on assertions inserted into the RTL code. When error conditions occur, the problematic portions of RTL are uploaded into Synopsys’ VCS simulator for offline simulation and debug while the main simulation run continues. Changes can then be re-verified in the hardware running on FPGAs.
A key aspect of the platform is Synopsys’ DesignWare IP library, which can be used for both the prototyping phase as well as the final SoC. This simplifies the process of implementing the SoC design in the FPGA-based prototype.
Finally, Synopsys is planning a series of educational half-day management seminars and full-day, hands-on technical workshops focused on rapid prototyping. For more information and to register, visit www.synopsys.com/Company/Pages/Events.aspx.
Synopsys