From cameras and flat-panel TVs to IC chip design and even IC transistor design, 3D is the buzzword these days, and authors aren’t always clear about what aspects of 3D they’re really covering. I’d like to look at the current state of 3D IC (chip) packaging. In particular, let’s look at 3D die-on-die stacking techniques, and a variation called 2.5D die-on-silicon interposer packaging, both of which face their own realities of implementation.
2.5D multi-die packaging uses passive silicon-based interposers (substrates) to horizontally connect multiple chips, with IC-scale electrical routing between the die. Through-silicon vias (TSVs) within the silicon interposer are used to route power and signals from the underlying substrate (such as a printed-circuit board), through the silicon substrate to the metal layers of the interposer, which then connect to the chips above through microbumps. TSVs also conduct a significant amount of heat out of the ICs to dissipate in the surrounding structures. Figure 1 illustrates a 2.5D package using a silicon interposer with TSVs and flip-chip bumps (also known as controlled collapse chip connection, or C4, bumps).
A full 3D package has multiple chips stacked vertically (Fig. 2). Here, TSVs are used within the active die to create connections from the front to the back of the chips though the silicon substrate. The chips are stacked on top of each other and connected through microbumps. The bottom chips are attached to the package substrate through C4 bumps.
Why go to 3D-IC? Increasingly, traditional 2D layout and packaging approaches are stressed to meet performance and form factor needs. The industry can use 3D designs to increase both data throughput and the amount of functionality in a given footprint. By going to 3D (or 2.5D), the connections between any two given points can be made shorter with lower parasitic resistance and capacitance values compared to traditional packaging approaches. This increases bandwidth and allows smaller drivers for inter-chip communication, which reduces power dissipation significantly.
Due to the density of interconnects, 3D packaging enables significantly wider buses, further increasing communication bandwidth. It also allows designers to combine chips using different technologies (e.g., different process nodes, or types) into a single multi-chip package with similar performance and footprint (heterogeneous technology integration).
In fact, there’s an example of form factor reduction already in production—CMOS image sensors are an early form of 3D-IC implementation. Designers have taken the image sensor and flip-chip stacked it directly on top of the logic that controls and performs some of the initial data processing for each pixel in that image sensor. Stacking creates a much shorter wire run length from sensor to logic and lets designers use a larger image sensor cell, providing a nice performance improvement and a much smaller form factor for the entire assembly, compared to using separately packaged chips for each function. There have also been pilot production offerings for some memory-on-logic applications using 3D-IC.
If 3D-IC products are so great, why isn’t everyone jumping into 3D technology with both feet? 3D-IC does promise significant value for a number of key industry issues, but it will be some years before die-on-die stacking becomes common outside niche applications. Several challenges have to be overcome first.
3D-IC structures involve challenges related to mechanical stress (Fig. 3), which has two sources.
First, die targeted for 3D-IC must be made extremely thin because there is a limit to the length of TSVs that can be reliably fabricated. We’re bonding these “thinned out” die together with solder balls, which slightly warp each die (especially if they aren’t distributed equally), resulting in a “potato chip” effect that induces mechanical stress. Stress changes transistor performance in the die in subtle ways that need to be modeled and understood.
Second, some of the die (which contain active transistors) have a TSV going through them. Each TSV induces stress and potential coupling effects in its vicinity. As an industry, we need to figure out how to design 3D-ICs to minimize or avoid these sources of stress, maybe by making changes to where we place transistors, or how we design them, so they’re either insensitive to or moved away from high-stress areas around large TSV macro structures.
With today’s traditional packaging, there’s a die with a heatsink on top, which dissipates the heat. With multiple die stacked in a 3D-IC, thermal dissipation may be a serious concern. Stacking multiple die on top of each other creates a die “sandwich,” where the layers in the middle (that don’t actually touch anything) can’t get rid of their heat. This creates major thermal challenges, since it is difficult to conduct the heat away from die inside the sandwich. In addition, if “hot spots” in multiple die in a stack line up, there could be local overheating problems (Fig. 4). As an industry we need to determine what thermal modeling is necessary to understand how these die interact with each other, so we create products with high reliability that don’t “melt.” Melting is great in a grilled cheese sandwich but not so much in your ICs.
Many of the testing issues echo those of thermal modeling. After a chip is built, but before it is placed in a package, it is put on a tester to determine, by touching test ports on the die, if it works correctly. With 3D-IC structures, the second through nth die are stacked on top of the first die, leaving no way to contact the stacked die for testing. The EDA industry has initiated a strategy for testing the die in the middle as we build our 3D sandwich, but its effectiveness awaits verification in high-volume production. There are also many test cost issues that need to be optimized to ensure good economics for 3D-IC manufacturing.
Design And Verification
In current design and verification flows, designers use a place-and-route tool, design whatever transistors are needed in the chip, perform design rule checking (DRC) runs on the chip to ensure it’s manufacturable, and call it done. In a 3D-IC world, there are interdependencies between the different die, especially if part of a logic circuit is on one die, and part is on another.
Tools from implementation to simulation need to understand what’s on each chip, how they’re connected together, what the timing delays between the two chips are, and so on. These new requirements significantly increase the complexity of figuring out how to design these chips. While physical verification has already solved that problem, there is still much work to do elsewhere.
What The IC Industry Will Do
There’s a lot of promise in 2.5D and 3D-IC technologies, but the industry still needs to solve a lot of hard problems. In the meantime, the industry will keep moving forward, so what are we going to do? Engineers and business managers are a conservative bunch, and none of us want to bet our next design (or our careers) on more risk than we have to. While many pundits say scaling is dead and everyone is going to 3D-IC, I believe the IC industry will pursue dual strategies for advanced design scaling and designs.
Moore’s law scaling (making transistors and wires smaller, putting wires closer together, etc.) will continue to be the dominant path forward for digital ICs, until it is either technically or economically unfeasible to do so. Using multi-patterning, there is a clear path to 14 nm without needing to move to more exotic technologies, such as extreme ultraviolet lithography or direct-write E-beam. The foundries are reporting that the ramp to volume at 28 nm is faster than 40 nm. So even with higher costs per wafer, as we always see node over node, the industry still sees value moving on with this path.
Simultaneously, the industry is going to be working on solving the problems of moving to 3D-IC. The first chips aren’t going to go straight to die-on-die stacking, though. Instead, they will use 2.5D die on silicon interposer, precisely to avoid many of the issues we’ve discussed. Not putting TSVs in an active die, but only in a silicon interposer (without active circuitry), eliminates the stress problem for active transistors.
You also don’t have the “sandwich” problem, so thermal will be less of an issue. And, you avoid the issues with testing stacked dies by building and testing the individual die, then packaging them side by side so you still have test access to all the chips. By pursuing a 2.5D-IC strategy, design teams can still design and verify the individual die as they always have, largely using the same 2D EDA flows they use today.
There have been some niche adoptions of flip-chip applications, such as the CMOS image sensors. For the vast majority of other early adopters, their early 2.5D applications will be large-area FPGAs and memory-on-logic (DRAM stacked on CPUs, GPUs, and SoCs). These products will be first because they see the biggest leverage from the jump in bandwidth between processors and memory, while minimizing overall die area as much as possible. They also benefit from reduced power and overall package size compared to traditional wirebonding packaging approaches.
Adopters can gain these benefits with 2.5D while continuing to leverage most of their existing 2D-IC design and verification flows. They can design independent die as they do today, then identify the system netlists of the entire 2.5D assembly, extract out the interface layers, and perform DRC, layout versus schematic (LVS), and parasitic extraction (PEX) on the interfaces.
The industry will get there, and full stacked die 3D-IC will eventually become mainstream, but it is still some years out. We’ll have a go at 2.5D first, buy some time to work out some of these issues, and build confidence and experience in stacking technologies.