Most high-speed printed-circuit-board (PCB) designers are familiar with simulating the performance of the laid-out and routed board. Still, one question pops up time and time again: “What can you simulate before you lay out the board?” This article will explain the differences between pre-layout and post-layout simulation, as well as answer the above question.
Table of Contents
- Simulating PCB Designs
- What Can You Simulate Before Laying Out The Board?
- Post-Layout Confirmation
Success in electronic design often hinges on running simulations. Whether signal integrity, power integrity, electromagnetic compatibility, analog, or even thermal simulations, they reveal information about design feasibility, margins, and limitations. We may perform simulations both before and after board layout, with different purposes, but the goal remains the same—to drive design changes.
The main difference between pre-layout and post-layout is that pre-layout simulations take place before completing the PCB layout, while post-layout simulations use the completed PCB layout as their basis. With signal-integrity simulations, for example, that means exact lengths of traces can be used in the post-layout analysis. Furthermore, criteria such as proximity of traces to via antipads and other plane voids also can be included in the analysis, depending on the amount of detail.
In pre-layout and post-layout, we translate physical parameters into circuit elements and other mathematical models for simulation. However, for pre-layout simulation, we must build up a circuit schematic to include all elements of the simulation. For signal-integrity purposes, this includes IC buffer models, package models, trace models, vias, discrete components, and any connectors and cables. In terms of power integrity, this includes plane shapes, stitching vias, capacitors, power sources, and loads (ICs).
Post-layout simulation involves extraction of physical information from the routed board. Items like traces, planes, and vias with defined geometries are automatically modeled, as are simpler components such as discrete devices. We add models for the ICs, connectors, and other connected components to run simulations. In each case, these user inputs are translated into a simulation schematic used by the simulator. Moreover, both types of simulations have the same simulation results. For signal-integrity simulations, the results appear as time/voltage waveforms that identify signal quality and timing information, and they can be displayed as waveforms or tables of data.
The main purpose of pre-layout simulation is to develop design constraints, while post-layout simulation’s main goal is to verify compliance with those constraints. Constraints can be relayed to the board designer in numerous ways: as Word documents; as automatic constraints built into the schematic and layout tool; or even written on a napkin. Design constraints serve to ensure that the board design is successful. As such, a variety of tasks must be undertaken in relation to pre- and post-layout simulation (see the table).
Take, for example, a length constraint. Many different electrical constraints can drive the length constraints—perhaps meeting some timing requirement or the need to control the amount of loss for a signal. For example, pre-layout simulation could help determine the maximum length of a serializer/deserializer (SERDES) signal by varying the length of the trace until there’s a closed eye diagram at the receiver.
An eye diagram is a display of multiple bits overlaid on top of one another in the same time interval to show worst-case conditions of a bit stream (see the figure). The same eye-diagram simulation would be run on the completed layout to ensure that the eye is still open.
Pre-layout simulation also serves to prove out board-level design concepts. Suppose that a certain hardware design calls for long-distance routing of a bus through several boards using several connectors. A pre-layout simulation shows if such a configuration allows for a signal at the receiver that meets the design specifications. Also, with pre-layout simulation, the engineer can understand the limitations of the buses in the design and create a plan to successfully implement those buses.
Post-layout simulation, on the other hand, is mainly used to verify the completed design. It verifies all design constraints after their creation. Post-layout simulation also comes in handy when comparing simulation versus measurements. This is important to ensure that the constraints created by pre-layout simulation are based on sound modeling of the PCB.
Troubleshooting is another useful application of post-layout simulation. When identifying a problem with a prototype in the lab, post-layout simulation serves to investigate possible causes of the issue. Once identified, exploratory simulation (usually performed in the same what-if environment as pre-layout simulation) can be used to find a solution.
Simulation and analysis experts tend to agree that most simulation work should of the pre-layout variety. This is good advice, because design changes tend to be costlier further into a design cycle. Specifically, any changes made after completing the layout can cost 10 times more than if they were avoided in the first place. The cost of changes made after prototyping can increase by another factor of 10.
Even so, finding a problem early in the design cycle using post-layout simulation is still orders of magnitude less expensive than trying to fix a shipping product. Whether the preference is pre-layout simulation, post-layout simulation, or a combination of both, it’s clear that without either, the risk of design failure escalates dramatically. Simply put, simulation is vital to understanding your PCB design, and designing reliable, successful products.
These articles and white papers contain more in-depth descriptions and analysis of both pre-layout and post-layout simulation.
- “Fundamentals of Signal Integrity Analysis”
- “Power Integrity In Systems Design: Part 1”
- “Established Confidence in PDN Simulation”
- “Designing PCBs with High-Speed Constraints: Developing Constraints”
- “Saving Time With Analog Simulation”
- “Simulation: The Need for Speed,” Timothy Coyle
- “BTS-314 Essential Principles of Signal Integrity,” Eric Bogatin
- “BTS113 Establish Confidence in PDN Simulation,” Eric Bogatin
- “BTS031 Chapter 1 of Signal and Power Integrity Simplified,” Eric Bogatin