There is no such thing as pure “digital,” which became clear in the early 1990s when “signal integrity” problems began to appear frequently. That’s when we began seeing signal speeds high enough that the traces on a printed-circuit board (PCB) became a significant part of the circuit. From then on, we began analyzing digital buses with respect to their analog characteristics. More recently, the power supplied to those digital circuits has become of greater concern, bringing rise to “power integrity” analysis. This article discusses the differences between these two types of analyses and how they lead to successful design closure.
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In the very early days of electronics, the only circuit long enough to behave like a transmission line was a telegraph line. Since then, edge rates have gotten quite a bit faster, to the point where the traces on a PCB are on the same order of length as the edge rates passing through them. For example, edge rates are now 100 ps and faster, which is close to half an inch (500 mils) on a PCB. As such, we must consider PCB traces to be transmission lines and analyze them for “signal integrity.”
Similarly, there once was one power pin and one ground pin on an integrated circuit. Most chips ran on 5 V, some on 3.3 V. In addition, if there was any extra “noise” on the data outputs of those ICs, you could connect a capacitor between the power and ground pins.
Modern ball-grid arrays (BGAs) boast hundreds of power and ground pins and have more than 10 different supply voltages ranging down to less than 1 V. They also are pulling tens of amps of current. Providing “clean” power to these ICs requires a huge network of capacitors. In turn, this has necessitated an understanding of how energy propagates through the power distribution network, which includes capacitors, stitching vias, and power/ground plane pairs, also known as “transmission planes.”
Thus, emerging analysis types distinguish between signal integrity and power integrity (see the table). In the sections that follow, we will make those distinctions clearer.
In signal integrity analysis, we start with a transmission line (Fig. 1a). There are many types of transmission lines. Coaxial cable, twisted pairs of wires, and traces above planes are but a few examples. On a PCB, we are concerned with traces above planes. Such transmission lines, or T-lines, have characteristic impedances, delays, and losses. Their characteristics determine how the connected I/O buffers interact with one another.
We may model most traces as a uniform two-dimensional cross-section. That cross-section is sufficient to calculate the characteristic impedance of the trace, which, in turn, will affect the shape of the waveform at the receiver on a signal line. The most basic signal integrity analysis involves setting up a board stackup, including appropriate dielectric layer thicknesses, and finding the proper trace width that corresponds with the target impedance for the traces.
When it comes to power integrity analysis, we are dealing with energy and its distribution through transmission planes (Fig. 1b). This immediately makes the analysis more complex than basic signal integrity, as we are now concerned with energy moving in x and y directions, as opposed to just one direction down the transmission line.
However, the goal of power integrity analysis is similar to basic signal integrity: to find the impedance of the power distribution network (PDN). In signal integrity, we are trying to match the impedance of a trace to a certain value, often 50 Ω.
To achieve good power integrity, we want the PDN to have the lowest impedance possible. At dc, that means having as low a resistance as possible in the plane shapes. At ac, that means minimizing the impedance between power and ground. That impedance will vary based on where on the board you are—where you place capacitors, how they are mounted, and what type and value of capacitor you use.
In fact, finding that impedance at different locations on the board is often the biggest part of the task in power integrity analysis. Often called decoupling analysis, the goal of this exercise is to find the impedance between power and ground at different locations on the board, usually at the power pins.
There is a simple version of decoupling analysis usually known as lumped analysis, in which we calculate the impedance of the PDN as if it were one node. This is usually a good, quick, first-pass type of analysis to ensure that there are enough capacitors and that they are the right values. Then, running a distributed analysis ensures that we meet all the impedance needs of the PDN at various locations on the board.
Most signal integrity analyses go beyond just a simple impedance calculation. However, the right impedance and other transmission line characteristics are essential to generating accurate results. There are three main types of simulations performed for signal integrity: signal quality, timing, and crosstalk.
To run a signal quality simulation, we add models for the driver and receiver (I/O buffers) to the transmission line, or PCB trace, model (Fig. 2). These models include information about the buffer impedance, edge rate, and voltage swing. Often, we use IBIS or Spice models as the buffer models.
With these models added, you can run simulations to determine what the signal will look like at the receiver. The goal is to get signals with nice clean edges, with no excessive overshoot or ring back. Often, we may solve these problems by adding some type of termination to match the impedances of the driver to the transmission lines.
Another application of such simulations is to determine the flight times of the signals as they travel around the board. Board timing is an important part of the system timing. The lengths of the lines, the propagation speed of signals as they travel through the board, and the shape of the waveform at the receiver all affect it. Because the shape of the waveform determines when the received signal crosses the logic threshold, it is essential to the timing. These simulations usually drive changes in the length constraints put on the traces.
Crosstalk is another often-run signal integrity simulation (Fig. 3). It involves multiple transmission lines coupled to one another. As we pack traces into dense board designs, knowing how much energy they are coupling onto one another is essential to eliminating crosstalk errors. These simulations will drive minimum spacing requirements between the traces.
In power integrity analysis, the main types of simulations are dc voltage drop analysis, decoupling analysis, and noise analysis.
First, dc voltage drop analysis involves the analysis of complex trace and plane shapes on the PCB to determine how much voltage is being lost due to the resistance of the copper (Fig. 4). The solution to dc voltage drop problems is simple: add more metal. This additional metal may take the form of wider and/or thicker trace and plane shapes, additional planes, or additional vias.
Decoupling analysis, which was discussed above, is aimed at determining and minimizing the impedance between power and ground at various IC locations on the board. Decoupling analysis usually drives changes in the value, type, and number of capacitors used in the PDN. As such, it requires models of the capacitors that include their parasitic inductances and resistances. It can also drive changes to how the capacitors are mounted and/or changes to the board stackup to meet the low impedance requirements.
The targets of noise analysis can vary. It can include noise from the IC power pins propagating around the board, which we control with the decoupling capacitors. It can be an investigation of how noise is coupling from one via to another. It also can be an analysis of simultaneous switching noise. In all cases, however, the ultimate goal of these analyses is to drive changes to the PDN: power/ground plane pairs, traces, capacitors, and vias.
All types of analysis are related. As PCBs become more complex, the lines between different realms of analysis become blurred. Even now, power integrity and signal integrity are closely related. Power integrity problems in a design can actually appear as signal integrity problems. That is why performing power integrity analysis and understanding the system margins of the PDN are important to creating successful, reliable designs and understanding and troubleshooting possible issues found in the lab.
Co-simulation between the two realms of analysis is a growing area, but the computational resources required and lack of modeling available have limited that progress. At present, it is usually more practical to analyze signal integrity and power integrity separately.
Signal integrity analysis continues to evolve. Now, it is often combined with 3D electromagnetic modeling for analysis of gigahertz-range serializer/deserializer (SERDES) buses to include detailed models of non-uniform trace structures, vias, packages, and connectors. In addition, we are performing new types of analysis, such as worst-case analysis and bit error rate prediction, on these very high-frequency SERDES buses. Its relationship to signal integrity will likely drive the evolution of power integrity analysis.
Someday, we may be able to simulate all disciplines of analysis simultaneously, creating “virtual prototypes” of our PCBs to gain complete insight into their performance before building them. This will include integration of signal integrity, power integrity, analog analysis, 3D electromagnetic analysis, and thermal analysis. As these disciplines continue to grow, they will continue to merge, all the while serving to help us understand our design limitations and drive design changes.
- Fundamentals of Signal Integrity Analysis
- Power Integrity Effects of High Density Interconnect (HDI)
- Signal Integrity Basics for PCB Engineers Series
- Signal Integrity Basics for PCB Engineers Series #2
- Solving IR Drop Challenges for Effective Power Delivery
- Optimize Power Delivery with Effective Decoupling