The PSoC 5LP family (see figure) is pin-for-pin replacement for the PSoC 5 although given the reconfigurability of the chip this is a relatively easy task even if the new chips had been altered in that fashion. Like the PSoC 5, the PSoC 5LP is based on a hard core Cortex-M3 with on-chip SRAM, EEPROM and flash memory plus reconfigurable digital and analog subsystems. The ability to reconfigure the subsytems allows designers to tailor the peripheral complement to their needs. It also allows a particular chip to be used in a range of applications with varying peripheral requirements.

Initially the chip will have a 67 MHz Cortex-M3 core. There will be an 80 MHz available later in 2013. The process has 1 Kbyte of cache and up to 256 Kbytes of flash, 64 Kbytes of SRAM, and 2 Kbytes of EEPROM. More compact versions are available as well.

The Universal Digital Block array contains a set of functional units that can be configured and connected in a variety of ways. It is less flexible than an FPGA but more powerful than a PLD and much easy to program. PSoC Creator, Cypress Semiconductor's graphical configuration tool, makes this job a matter of menu selections and drag-and-drop connections (see PSoC Development Software).

There are a few fixed function blocks on the digital side depending upon the SKU. The family supports CAN 2.0 and USB 2.0 with on-chip PHY.

The analog subsytem is similar in terms of user configuration. The high end PSoC 5LP includes a digital filter block (DFB). The 12-bit SAR ADC rivals many standalone SAR ADC chips. It can now handle 1 Msample/s. There is also a 20-bit Delta-Sigma ADC and up to four DACs. The CapSense capacitive touch support is in the analog subsystem.

The new architecture is designed for low power operation but its power flexibility is equally important. The chips have four isolated voltage domains allowing peripherals to interact with devices at their native voltage range. The domains are specified in PSoC Creator when a chip layout is designed. The analog side of the chip operates between 1.61V and 5.5V. There ia a 1.024V +/-0.1% internal reference voltage for the op amps and comparators.

The PSoC 5LP can operate between 0.5V and 5.5V. An internal boost systems allows 0.5V operation. The chip only requires 300nA in hibernate mode.

Earlier this year Cypress Semiconductor updated its PSoC Creator. This was a major improvement adding user interface features like rubber banding when moving interconnected blocks. It comes with over 80 pre-verified components. Cypress is also periodically releasing updates with additional components. Of course, designers are free to create or enhance components to fit their needs. It is also possible to connect components together to eliminate processor overhead.

The PSoC architecture has always provide designers with flexibility not found in other platforms. It allows a single chip to address a range of applications and configurations. The PSoC 5LP continues in this tradition and puts it in new low power applications as well.