If it’s not residing at the top, energy efficiency has been elevated into one of the primary advanced IC design issues, particularly in battery-powered portable applications such as cell phones, GPS, PDAs, and tablet PCs. Steady market expansion of these applications, with no sign of it stopping in the foreseeable future, pushes designers even harder to find solutions.
Technology scaling has significantly increased device leakage current. Consequently, the reduction of static power consumption in idle devices is as important as lowering the dynamic power consumption of active devices. In practice, dynamic voltage scaling (DVS) and power-gating techniques with various power-mode definitions can reduce both dynamic and leakage power. But with dramatic increases in power domains and power modes, it becomes more difficult to manually define interface rules (e.g., level shifter and isolation cell) for each domain crossing.
To address these problems, a “power-mode-driven” design methodology is proposed to automatically generate a proper interface rule, rather than rely on a “rule-based” approach like Common Power Format (CPF) or Unified Power Format (UPF). We also propose a “seamless” interface control circuit for DVS to be used with power-gating designs. Experimental results based on state-of-the-art industrial designs demonstrate the framework’s efficiency when handling large-scale designs with more than 50 power domains and 80 power modes.
Table of Contents
- Power-Gating/ DVS Design Background
- Multi-domain MTCMOS And DVS Design
- The Proposed Framework
Power gating represents a promising approach to effectively controlling leakage. It essentially cuts off the supply voltage to a gated block when in an idle state and resumes the supply voltage when entering an active state.
Power gating can be implemented using off-chip or on-chip control (Fig. 1). Off-chip power gating turns off the supply voltage to the power-gated domains (e.g., blocks V1, V2, and V3) with a voltage regulator on board. This approach suits long-term power shut-off because it may take a long time to restore power to the gated blocks. On-chip power gating can turn off the power sources through switchable power pads (e.g., block V2) or power switch cells (e.g., block V3). Turning off a power source through switchable power pads is quite simple, but it needs extra I/O space for the pads, and it isn’t suitable for pad-limited designs. In addition, it lacks the flexibility to control power-up time and the rush current to the turned-off blocks.
Recently, multi-threshold CMOS (MTCMOS) technology has emerged as the most popular power-gating design methodology. MTCMOS designs use high-VT transistors to build always-on circuits (e.g., power switches, retention flip-flops, and always-on buffers) to further reduce leakage during idle mode. At the same time, low-VT transistors can maintain performance during active mode.
For some applications, state-retention power gating (SRPG) may retain the state of flip-flops or memories while the power supply of the corresponding block is shut off. Gated blocks turned off in standby mode will consume only a little leakage, since the blocks are gated by high-VT sleep transistors.
A simplified block diagram of an embedded processor helps demonstrate the practice of DVS and state-retention power gating (SRPG) (Fig. 2). The design is partitioned into three major blocks: VSOC, VCORE, and VRAM. TVDD_SOC supplies VSOC with a fixed voltage of 1.2 V. VCORE incorporates a dynamic voltage supply with on-chip power gating through power switch cells, where TVDD_CORE is the true power supply and VDDV_CORE is the virtual power supply. While VCORE is shut off, SRPG cells are used in place of normal flip-flops to keep the states of some flip-flops. TVDD_RAM supplies VRAM, which may dynamically change the supply voltage (varying from 0.9 to 1.2 V, based on performance and power requirements).
VCORE and VRAM might dynamically change the supply voltages at different power modes (Table 1). For example, turning off the pMOS MTCOMS shuts off VCORE, and supplying VRAM with the lowest voltage (0.9 V) in Sleep and USleep modes saves power consumption. However, they’re both supplied with 1.2 V in full-speed mode to achieve performance requirements. Modeling the low-power design intent of a chip for implementation and verification typically involves adopting a common power format (e.g., CPF or UPF). As a flexible ASIC company, Global Unichip Corp. supports both formats.
One major challenge associated with multi-domain MTCMOS and DVS designs involves placing correct interface logic (e.g., isolation cells and level shifters) on the interfaces between power-on and the power-off blocks and keeping the interface logic at determinate states without floating nodes. Verification presents a rather sturdy challenge to chip success, too. A DVS and power-gating design may fail due to structural errors such as a missing isolation cell or level shifter, incorrect propagation of sleep control, and/or incorrect power domain connection.
Comprehensive low-power verification should include electrical check, power-aware formal verification, sleep-control functional correctness, IR and EM analysis, voltage ramp-up time, and inrush current analysis. Increasing power domains and power modes complicates level shifter and isolation cell planning, as well as verification of DVS and power-gating designs, due to the overwhelming number of dependencies within the power domains.
Power domains may operate with different voltages in different power modes (Table 1, again). It’s necessary to place proper interface logic, such as an enable shifter (low-to-high or high-to-low level shifter with output clamping), or isolation cells (output clamping) between the off-to-on interface to avoid leakage currents that result from an unknown state (Fig. 3). Enable shifters and isolation cells are widely used in power-gating designs and fully validated in production.
Some mobile-phone applications feature new interface logic that performs data latch and possesses level-shift and isolation functions. The requirement for this logic is that the active domain doesn’t experience a data change of its source domain, whether the domain is powered on or off.
In practice, the rule-based design methodology is precarious and, to a certain extent, impractical for a state-of-the-art industrial multi-domain MTCMOS and DVS design that includes dozens of power modes. Consequently, interface rules need to be described one-by-one per domain crossing.
According to the power-domain and power-mode specifications given in Table 1, an interface plan is required to select proper interface logic so the design works correctly for each power-mode transition. Table 2 illustrates an effective interface plan for an embedded processor. Each grid in the table reflects a domain crossing. The interface plan covers all possible 4-by-4 domain crossings, where LH, HL and LHC stand for low-to-high level shifter, high-to-low shifter, low-to-high shifter with output clamping, high-to-low shifter with output clamping, and isolation cell, respectively.
In Table 2, “-” indicates that there’s no need for interface cells. VCORE could be powered off and VRAM works at 0.9 V in both USleep and Sleep modes. Therefore, isolation cells are required for domain crossing from VCORE to VRAM. In addition, when the processor operates in USlow, Slow, MSlow, and Medium modes, the VCORE voltages are lower than VRAM voltage. As a result, it needs low-to-high shifters (HLs) for domain crossing from VCORE to VRAM. Consequently, low-to-high shifter with output clamping (LHC) interface logic is needed from the VCORE-to-VRAM interface.
It’s not difficult to derive an interface plan for 4-by-4 domain crossings with seven power modes. But when considering a real 4G smart-phone design as an example, it’s not unusual to have more than 50 power domains and more than 80 power modes.
Looking at a power-domain and power-mode description for a smart-phone application, each grid reflects a proper voltage level (Fig. 4). It’s impractical to manually develop an interface plan by examining 80 power modes for each of the 50-by-50 possible domain crossings. Thus, it becomes critical to define a low-power design specification for chip implementation and verification.
There are 2500 possible domain crossings converted from the rule-based low-power design specification (e.g., CPF or UPF) for 80 different power modes and 50 power-gated domains. Each can be switched off individually (Fig. 5). Does this mean we need to review 80 power modes, specify 2500 interface rules, and then create 2500 isolation enable signals? In practice, nearly 90% of the total domain crossings don’t need interface logic because they are irrelevant.
Usually, designers only specify the major concerns for power domains in the interface plan based on their understanding of the RTL design. For ambiguous domain crossings, designers may assign incorrect interface logic, which causes difficulty following the implementation and verification stages. Furthermore, additional cross-domain paths may be created after design-for-test (DFT) implementation. Consequently, the interface plan must be reviewed after DFT implementation to ensure the interface logic is complete.
Currently, most low-power design and verification tools are based on CPF or UPF. Designers thus must provide a clean and complete CPF or UPF before implementation or verification. Take, for example, a rule-based low-power design specification for an embedded processor (Fig. 6). In addition to power domain, power mode, level shifter, and isolation cell definitions, one has to define complete interface rules, including level shifter rule and isolation rule, for all domain crossings.
Domain crossing from VCORE to VRAM uses “create_level_shifter_rule” and “create_isolation_rule” to define a proper interface cell (Fig. 6, again). As power domains and power modes increase, though, it becomes impractical to manually describe all interface rules. Unfortunately, no commercial tool, like a CPF or UPF compiler, exists to deal with such a burden. Besides, EDA tools might come up with incorrect results if the CPF or UPF is incomplete and unclean.
When powering off the low-voltage domain in a latch-based enable shifter design, signal SLEEPB will issue a transition from high to low earlier in the process (Fig. 7). Then, signals EN2 and EN1 will make transitions from high to low after the delays of d2 and d1, respectively, where d1 is longer than d2. By making d1 longer than d2, the latch QO will capture the value of ZO before the level shifter is disabled. When EN1 goes low later, the level shifter becomes disabled and the output ZO may be clamped to a constant value.
After EN1 goes low, VDDL_ACTIVE activates and disables the pMOS header switches to turn off the power source VDDL. During power-up of the low-voltage domain, on the other hand, signal SLEEPB transits from low to high, and signal EN1 transits to high after a delay d2 and activates the level shifter. Likewise, signal EN2 transits to high after a longer delay d1.
Signal VDDL_ACTIVE designates whether or not the low-voltage domain is active. At the least, the low-voltage domain should be disabled after the state of latch is held earlier via signal EN2. When powering on the low-power domain, signal VDDL_ACTIVE preferably activates the low-voltage domain before signal EN2 makes the latch transparent to avoid glitches at latch output QO.
The “power-mode-driven” design concept is a suggestion as well as a design flow improvement for power-design specification, chip implementation, and verification. To the best of our knowledge, CPF or UPF is an extension of hardware description language, and the interface rules should not be entirely enumerated or changed throughout the design flow. According to the proposed power-mode-driven design methodology, most of the necessary interface rules can be derived efficiently and automatically. The low-power intent (CPF or UPF) can be described correctly and concisely. A few remaining interface rules act as constraints.
Figure 8 shows the associated pseudo-code of the proposed framework. We could perform interface planning automatically to derive complete interface rules with proper control binding in common power formats (CPF or UPF) for chip implementation, via a simple power-domain and power-mode definition.
A complete interface plan was derived to cover all possible 50-by-50 domain crossings according to the design intent (Fig. 9). Different legends (e.g., LHC, HLC, LHD, HLD, ISO where LHC, HLC, LHD, HLD and ISO stand for one low-to-high shifter with output clamping, high-to-low shifter with output clamping, low-to-high shifter, high-to-low shifter and isolation cell, respectively) in the sheet reflect a proper interface cell type, and “-” means the interface is unnecessary for this domain crossing.
The major interface rule is based on the actual signal crossings from the gate-level netlist (Fig. 10). From the aspect of signal crossing, what’s expected is a sparse matrix (only 84 rules), which should be the minimum requirements provided by designers. As a result, there’s no need to specify 50-by-50 or 2500 interface rules with almost 2500 low-power controls. Since a major power format template based on the signal crossings from the netlist can be derived, all that’s required is to associate the actual controls of a power-management unit.
Based on the proposed interface plan algorithm, it’s possible to identify the rules already specified in a customer’s power intent (CPF or UPF) and whether or not the design specification matches what was expected. Figure 11 shows a manual interface rule in matrix format and the coverage analysis between the manual interface rule and what was expected. An incremental interface rule can be derived after DFT insertion, design rule fixing, and timing fixing. Each pink node implies that the original interface rule is incapable for the new domain crossing after performing DFT insertion, DRV fixing, or timing fixing.
In addition to electrical verification, it’s possible to proof the function correctness of low-power control formally before logic simulation. (That’s because the necessary interface plan, automatically based on a simplified domain/mode setting during chip implementation, can be derived.)
Except for structural check, it’s important to verify the functional correctness of sleep enable, isolation clamping, retention control, and other test signals. The necessary low-power controls, separated in different rule descriptions, could be extracted and then combined into a set of controls for each power mode based on the specified CPF or UPF file (Fig. 12). Consequently, most power-domain and function errors can be identified before entering the logical simulation by formally verifying the low-power control (Fig. 13). In addition, the functional correctness could be proofed statically from the finite-state-machine (FSM) register’s output if designers can provide the associated control values.
Power-gating design has seen extensive usage in recent years. About five years ago, power gating through off-chip voltage regulator control was particularly popular. However, the popularity of MTCMOS power gating methodology has led to a dramatic rise in the number of power domains and power modes. More customer projects request tens of power domains and power modes. Unfortunately, most commercial tools still aren’t mature enough to deal with such complexity.
This article presented a new interface control circuit that provides seamless operation between power-off and power-on domains. The circuit provides a data-latch function and possesses the capabilities of level shifting and clamping control without leakage path. Furthermore, a power-mode-driven low-power design methodology is proposed for automatic interface planning. It simplifies the interface rules required by complex power modes and power domains and helps designers generate a clean and complete interface plan for subsequent low-power implementation and verification.
- S. H. Chen and J. Y. Lin, “Experiences of low power design implementation and verification,” Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC), 2008, pp. 742–747.
- S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, and J. Yamada, “1V high-speed digital circuit technology with 0.5µm multi-threshold CMOS,” in Proc. IEEE 6th Int. Annual ASIC Conf., 1993, pp. 186–189.
- M. Keating, D. Flynn, R. Aitken, A. Gibsons, and K. Shi, Low Power Methodology Manual for System on Chip Design. New York: Springer, 2007, ch. 14, pp. 225–247.
- S. H. Chen and J. Y. Lin, “Implementation and Verification Practices of DVFS and Power Gating,” Proc. of VLSI Design, Automation and Test (VLSI-DAT), 2009, p.19–22.
- S. H. Chen, Y. L. Lin, and C.T. Chao, “Power-up Sequence Control for MTCMOS Designs,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, Nov. 2012.
- S. H. Chen, “System and Method for Power Domain Isolation.” U.S. Patent 7982498, Jul. 19, 2011.