Many unattended microprocessor devices require supervisory circuitry to guard against unintentional program interruption due to power spikes or other electrical noise. This simple circuit uses one CMOS Schmitt-trigger gate to generate such a "watchdog reset" function (see the figure, a). By employing the remaining three gates in the IC package, low-power nonmaskable interrupt and low-power reset functions can also be provided.
The basic circuit uses one-quarter of CMOS Schmitt-trigger U1 as a gated astable. In normal operation, the microprocessor supplies a square wave, which is ac-coupled through C1. Diodes D1 , D2 and capacitor C2 from a negative-going peak detector. As long as the pulses continue, C2 is kept charged and pin 2 of U1A is kept below the minimum high threshold voltage of 1.5 V, and the output of U1A remains high. If the microprocessor stops supplying a square wave, C2 discharges through R3, bringing the U1A input above its high threshold voltage and enabling the Schmitt-trigger astable. The astable then sends the microprocessor a series of reset pulses until normal operation resumes.
The full-fledged supervisory circuit is created by adding a "POWER OK" enable input to gated astable U1A (see the figure, b). When the POWER OK input voltage applied through the divider network R6 and R7 drops below the approximate 3-V maximum high threshold of U1C, the POWER FAIL and -RESET outputs are forced low. R5 and C4 delay the -RESET signal so that the microprocessor can execute a power-fail or reset routine before reset occurs.
The microprocessor should toggle the watchdog input 20 to 100 times per second with a 20 to 80% duty cycle; shorter pulses won't keep C3 charged. On power-up, the microprocessor should execute a routine that sends a 0.25 second or more of pulses to "prime" the circuit.
The microprocessor will be reset at a certain time interval after the watchdog pulses cease. This time interval is set by the network of C1, C2, and R3, to about 0.25 s to 0.5 s. R4 and C3 set the frequency of reset pulses to between 3 and 6 Hz. C4 and R5 set the time between when the —POWER FAIL INT line falls and the —RESET line fall to approximately 1.2 ms. All times will vary somewhat due to variations in the Schmitt-trigger threshold voltages.