This article is in Bob Pease on Analog Vol. 1 in the Analog section of the Electronic Design Library. 

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Once upon a time—my gosh, it was 30 years ago—a guy asked me if I could show him how to make a Frequency-to-Voltage converter (FVC). Well, at that time, at George A. Philbrick Researches, we knew a lot about analog computers and we figured we could convert almost any signal to any other form or mode. So I designed a charge-dispenser made of a voltage limiter, a capacitor, and diodes. I built it up, and it worked pretty well.

And in 1964 we put this into the old Philbrick Applications Manual.¹ (Fig. 1).

The first amplifier has a limited output voltage. The p-p voltage across the capacitor is pretty well established:

V p-p = 2V_z + 2V_d - 2V_d

So, the charge (Q = C × V p-p) flows through the feedback resistor of the second amplifier. The output voltage will be, on the average:

V_out = R_f × C × V p-p × f

A few years later, we got into the Voltage-to-Frequency Converter (VFC) business. At the same time, I came up with an improved circuit for an FVC (Fig. 2). The input comparator is set up to accommodate TTL signals, but if you put a resistor from the + input to -15 V, you can accommodate symmetrical signals; a resistor from the + input to ground will cut down the hysteresis and let you handle small signals.

But the real improvement in this FVC is the bleeder resistor, the 3.3 MΩ added to the right end of the capacitor. If you want a charge dispenser to dispense a constant amount of charge, no matter what the rep rate of the pulses, you can't let the voltage at the right end of the capacitor just sit there unattended. That's because it will be charged (through the nonlinear impedance of the diodes) to a different voltage, depending on how long you wait. The 3.3-MΩ resistor helps pull charge off that node, so the p-p voltage is always constant at high or low speeds.

That is what's required for good linearity—for minimum deviation from the straight line of:

V_out = k × F_in + (error)

Also, note the symmetrical Zener clamp.²

Another cute feature was the adaptive filter at the summing point of the second amplifier. The conductance of the diode is linearly proportional to the current through it, so the 1-µF capacitor gives an adaptive time constant and helps filter the signal more at low frequencies, less at high frequencies. That's the classical problem with most F-to-V converters: If you want to get low ripple, you get slow response due to the heavy filtering. If you want fast response, it's hard to get low ripple.

After I left Philbrick, I joined National and designed the LM131 voltage-to-frequency converter³, using completely different ideas than any of the Philbrick circuits. It used Q = I × T, rather than the Q = C × V employed by all of the Philbrick ones. It didn't need ±15 V; it could run on +15 or +30 or +12 or +5 V—much easier to apply. BUT, it still had the same constraint when you used it as an F-to-V converter: If you want low ripple, it's hard to get fast response.

In 1978, I wrote an application note on how to improve the response time of an FVC—in the Linear Apps Handbook.⁴ I showed how to cascade two or more fast Sallen-Key filters to give reasonably quick response, yet filter out the ripple at 24 dB per octave. For example, if you have a frequency in the range 5 to 10 kHz and the frequency suddenly changes, you can get the output voltage to settle to the new level (within 1%) in about 40 ms—that's about 200 cycles—yet the ripple will be less than 5 mV p-p. That's about a 10:1 improvement over a single R-C filter. Good, but not good enough for some applications.

In 1979, I wrote another App Note⁵ showing how to use a phase-locked loop to make a quicker F-to-V converter, about 2 ms. That's about 10 cycles of the new frequency—a further 20:1 improvement.

Not bad—but still not fast enough for everybody. For example, in a control loop, you may need a voltage that represents the frequency, and any delay or lag in the information may cause loop instability. So a fast response can be very important.

Recently, a guy asked me how to make a 60-Hz FVC with quick response and negligible lag or delay. I told him that the standard procedure is to use a fast clock and a digital counter. But the number of counts collected during one period is linearly proportional to the period of the signal, and you might have to do some digital computations to convert that to a signal representing the frequency. Then I realized that a "multiplying" DAC can be used to divide in a reciprocal mode.

The digital logic generates a couple of pulses at the time of each rising edge of the incoming frequency (you could use some kind of dual one-shot multivibrator, but I didn't have any of those around). The first pulse loads the data from the CD4040 into the DAC (the pulse also disables the path from the clock to the counter to avoid any confusion from rippling in the counter). Then the second pulse resets the counter.

The MDAC has storage registers built in, so the data from the counter is fed right in to the DAC when the WRITE-2-bar pulse is applied. The MDAC isn't connected in the normal way, with the variable resistance in the input path. The fixed resistor is in the input, and the impedance controlled by the Digital code is connected as the feedback resistor. This permits the multiplying DAC to act as a divider, so the reciprocal function is done neatly—not in the digital realm, and not in the analog world, but on the cusp between them. (More on this in a few months). The LM607BN was chosen for the op amp because you need low offset. It's cheap, V_os is only 25 µV typical (60 µV max.), and you don't need a trimmer pot.

The guy who asked me for this function was quite pleased, as he said there are several suppliers who are happy to sell you this function for a couple hundred dollars.

But it's really not that big a deal. You can do the whole thing yourself. All it takes is just a few dollars worth of parts and a little labor.

The main limitation of this scheme is getting a decent resolution on the output voltage if you must cover a wide range of frequencies. For example, if you have to cover a 10:1 range, let's say from 20 to 200 Hz, then you can only use a clock frequency of 20 kHz with a 10-bit counter (or the clock counter would overflow, giving unacceptable false answers).⁶ Then at 60 Hz, the number of counts would be just 333. The resolution would be only one part out of 333, or one-third percent.

So, if 200 Hz is scaled for 10 V, 60 Hz for 3 V, and 20 Hz for 1 V, then the FVC can only resolve the difference between 60.18 Hz and 60.000 Hz—for example, 3.000 V and 3.009 V. The resolution at 200 Hz would be even worse, about 100 mV per step, because there are so few COUNTS there.

If you need to get better resolution, you can get a 4X improvement by using a more expensive 12-bit MDAC and a 80 kHz clock. An 8-bit MDAC, even though the price is right, can't give much better than 1% resolution, even if you use it in a dynamic range of just one octave.

So, there's the limitation to this counting method. But you have to admit it is fast and has low ripple! (Of course, the other limitation is that if you wanted a fast computation for a 60-kHz frequency, you might need a 20 or 80 MHz clock and counter, not impossible, but not so easy....)

All for now./Comments invited! RAP/Robert A. Pease/Engineer

p.s. And in an upcoming column, I plan to write about Voltage-to-Frequency converters, too.

Read more article from Bob Pease on Analog Vol. 1.

References:

1. Teledyne Philbrick, Applications Manual, 1965, 1985; p. 95; (out of print).
2. How do you like that little Zener bridge circuit that's inherently symmetrical in its swing? As near as I can tell, it was first published by NSC in an "Applications Corner" in Electronic Design, p. 69, July 5, 1976. I sort of invented it about 1971—has anybody ever seen it before 1976? I don't think I have ever seen any patent on it—and if there had been one, it would have expired by now....
3. LM131/LM231/LM331 Voltage-to-Frequency Converter data sheet; available on request.
4. National Semiconductor Linear Applications Handbook; Appendix D, available on request.
5. Ibid., Application Note AN210.
6. That's the function of the trick circuit shown in Figure 3—to detect when the counter is nearly full, shutting off the clock. This prevents preposterous outputs when the frequency approaches zero.