While the quest for ever-increasing performance continues, it no longer does so at any cost—not since we slammed into the power wall. Power and performance now must be balanced, and numerous techniques have evolved for reducing power consumption at a given performance.

Such techniques used to focus on circuit design only—by optimizing transistor sizes, gating clocks, and other low-level tricks. But by the time the design gets to that stage, most of the power consumption has been determined already, and you’re just tweaking it a little when designing the circuit. The real payoff comes much earlier in the game: during architecture definition.

A Bigger Impact

Rather than toying with savings on the order of 5%, key architectural decisions can have a much more dramatic impact—tens of percent. One of the most effective approaches to come along is the use of power islands, which group entire portions of the circuitry with a single power supply. Neighboring groups have their own supplies, very likely at the same voltage.

Even though a system-on-a-chip (SoC) will “contain” all the circuitry required to do everything it will ever have to do, only a few of those circuits are needed at any given time. So, “islands” containing unused circuits can be set to some lower-power state.

Exactly what those lower-power states might be can vary dramatically according to the planned usage of the chip. They may have several such states, ranging from a sleep state to complete power down. It’s completely analogous to the way your laptop saves power—by shutting off the display after a while, perhaps shutting down the hard drive a bit later, or going into full hibernation if ignored for longer yet.

This is simple enough in concept, but it’s tricky to implement. One of the major assumptions of old-school circuit design is that VCC is always at a high voltage and ground is always connected at a “low” voltage. Violate those principles and all manner of bizarre things can happen as diodes forward bias and “sneak paths” appear.

It’s like filling a bucket of water on an upper balcony using a hose from down below. When you turn the water off, if you’re not careful, you may end up siphoning out all the water that you just pumped up there.

Just as cities typically require anti-siphon valves specifically so dirty water doesn’t end up getting siphoned back into the city water system, so isolation is required at power domain boundaries to ensure that the power rails behave well when cycling up and down next to neighboring circuits that may be at different power states. Verifying that this all works is a job for circuit simulation and power analysis, since it involves analog behavior on a time-scale far larger than what is typical for normal circuit operation.

But once the power rails themselves have been properly designed and verified, there is the issue of how well the actual circuitry of each island plays on its own and with its neighbors through the adjoining inputs and outputs.

This isn’t so much a matter of leakage currents and other analog behavior, but a simple result of the fact that, when an island is powered down, all the circuitry goes into an undefined state. How does the power island recover from that undefined state when powered up again? And how does the neighboring circuitry deal with that state? Does it ignore it, or are there unexpected problems?

The Right Plan

This isn’t a concern just for the static situation where one island is on and one is off. Circuitry can change values during the transitions when powering up or down. Any transient state that upsets the neighbors is a problem, and a thorough verification plan must incorporate tests that ensure that everything is well behaved regardless of the power states of the different power islands.

Critical goals of such power-aware verification can be accomplished even during emulation. Because an emulator only verifies logic, and not actual transistor circuitry, emulation won’t check for analog issues or leakage currents. They also lack the ability to create the specific power islands that will be used in an SoC, so actual power cycling of the islands in an emulator isn’t possible.

But it is possible to verify that the logic of the entire circuit can tolerate different portions of the circuit being in undefined states, either as a result of being powered down or as a result of being in transition from power-up to powered-down or vice versa. By intelligently randomizing states in accordance with the power intent expressed in, for example, a UPF file, an emulator with this capability can provide critical assurance that the circuit is robust in the face of these undefined states.

While power-aware emulation doesn’t replace full power analysis, it’s yet another easy-to-use tool to help build confidence in an SoC’s ability to perform unperturbed by the powering on and off of different parts of the circuit as designers strive to keep power dissipation as low as possible.