SystemVerilog Support Leads Debuggers' Upgrades

In the latest versions of its Debussy and Verdi debugging systems, Novas Software includes support for SystemVerilog, making them among the first debug systems to support the emerging standard.

The debuggers will work with SystemVerilog in much the same way they work with Verilog and VHDL. Users can read in results generated by SystemVerilog-based simulators and use the debuggers to quickly hunt down bugs and map them to the SystemVerilog source code. Other technology enhancements were made to the core platform for Debussy and Verdi, like database upgrades that use less memory and speed up many debug operations.

A new clock-tree debug and analysis capability enables users to easily detect and check clock-domain crossings. Users can also import Synopsys PrimeTime timing analysis reports into Debussy and Verdi. The debuggers automatically generate a list of the critical paths identified by PrimeTime.

Novas' assertion-driven debug capabilities, introduced in a beta version in March, have now been fully integrated for production use. The debuggers can browse and trace OpenVera Assertions source code along with HDL source code. They can display the results of assertion-based verification tools in both source and waveform views.

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