The demand for DDR3 memory channel bandwidth is growing rapidly in applications such as high definition video and TV, smart phones, and networking component. To meet these requirements, SoCs usually include a high bandwidth DDR3 memory channel. However, in a number of SoCs, many legacy component still need to access a normal DDR3 memory channel as well.
Some legacy component may interface with a DDR3 memory channel through a non-split transaction type bus protocol (such as AHB bus). SoC designers often create separate DDR3 memory channels to prevent the non-split transaction legacy protocol component from blocking those high bandwidth applications. This implementation, however, may significantly increase both pin count and design complexity.
To minimize pin count and simplify SoC design complexity, this article introduces a unified single DDR3 memory channel architecture that can simultaneously serve legacy component without creating performance bottlenecks.