Scalable DSP Core Brings Compilability To Lower-Cost Applications

Sept. 18, 2000
Taking advantage of a scalable strategy, the StarCore technology center has prepared a single-data-path ALU substantiation of its SC100 DSP architecture. Made on a 0.18-µm CMOS process, the SC110 offers a scaled-down number of function units,...

Taking advantage of a scalable strategy, the StarCore technology center has prepared a single-data-path ALU substantiation of its SC100 DSP architecture. Made on a 0.18-µm CMOS process, the SC110 offers a scaled-down number of function units, issue width, and bus width. As a result, it provides a low-power, low-cost alternative for entry-level consumer and communications applications.

The core is upward code-compatible with the powerful SC140, which was the first implementation of the scalable very-long-instruction-word (VLIW)-based SC100 architecture. The SC140 core comprises four 16-bit data paths, each of which contains a combined ALU, MAC, and a bit-field unit (BFU).

A single data path is offered by the SC110, however. Therefore, there's only one set of combined ALU/MAC/BFU (see the figure). In addition, the data-bus and program-bus widths in the scaled SC110 core have been reduced by half. Subsequently, the data bus and program bus dropped to 32 and 64 bits, respectively. As a result, the die area of the SC110 was narrowed by half and the peak power consumption was slashed to 90 mW at 1.5 V or 13 mW at 0.9 V.

This shrinkage means that processing performance is comparatively lower. At a 300-MHz clock frequency, the SC110 delivers 300 million MACs or 900 RISC MIPS.

Yet "the SC110 does not sacrifice the efficient compilability of the SC100 architecture," according to Scott Beach, StarCore's SC100 platform marketing manager. "It maintains the variable-length-execution set (VLES) flexibility of the fundamental architecture. It leverages the architecture's orthogonal instruction set for efficient compiled code and easier assembly programming for reduced time to market," he adds. The resultant compact code also cuts memory requirement to lower overall system cost. "In essence," he continues, "the SC110 brings efficient compilability to lower-cost, high-volume applications like Internet telephony, MP3 audio, and home networking."

StarCore is a cooperative research and development initiative between Lucent Technologies' microelectronics group and Motorola's semiconductor products sector. Developers at StarCore expect to deliver the new cost-effective core to Lucent Technologies and Motorola Inc. by the fourth quarter. The two StarCore partners, however, have not yet revealed their plans for the SC110 DSP core. Meanwhile, engineers at StarCore continue to develop other variations of the scalable SC100, in addition to a generation beyond the SC100. Details concerning these future programs were unavailable as this story went to press.

For more information on StarCore, visit www.starcore-dsp.com.

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