11 Myths About High-Level-Synthesis Techniques for Programming FPGAs (.PDF Download)

The numbers of applications using FPGAs are on the rise. They have long been used for avionics and DSP-based applications, but are finding many new applications in which their flexible and configurable compute capabilities are much in demand. These applications include accelerating large compute-intensive workloads, within wireless base control and management functions, and already look set to play a major role in vision processing in autonomous driving systems.

Their strength comes from the fact hardware developers can program it to deliver exactly what they need for their design. When they were students, many engineers might have learned that they can program FPGAs through the use of a hardware description language (HDL), the most popular of those being VHDL and Verilog.

An HDL is used to implement a register-transfer-level (RTL) abstraction of a design. In time, the process of creating RTL abstractions was made easier through the use of reusable IP blocks, speeding the design-flow process. As designs became more complex and the time-to-market pressures increased, developers and the vendor community have strived to provide more software-based tool chains to help reduce development times.

One of these techniques is “high level synthesis” (HLS). HLS can be thought of as a productivity tool for hardware designs. It typically uses C/C++ source files to generate RTL that is, in most cases, optimized for a particular target FPGA device.

Like many new ways of performing a task, a number of myths have evolved surrounding HLS. Let’s review them and understand how some of them have come about.