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The increase in content generated and consumed in today’s mobile systems puts higher demands on chip-to-chip interfaces that transfer data and multimedia content to storage subsystems. Content generated on mobile devices such as multi-megapixel image sensors and downloaded multimedia files and data require high throughput, high capacity, and scalable storage. The MIPI M-PHY specification, the MIPI UniPro specification, and the JEDEC UFS standard enable low-power and high-speed operation with the features and scalability required for high-end mobile systems, facilitating even faster adoption.

JEDEC UFS Overview

The JEDEC JC64.1 task group defined Universal Flash Storage (UFS) v1.1 as the standard interface for unifying all non-volatile memory (NVM) interfaces in mobile and consumer electronics. The group designed UFS to be the most advanced specification for embedded flash memory storage in mobile phones and tablet PCs. It developed the UFS standard because eMMC, the memory interface standard that had offered the best solution for most mobile devices, was unable to meet the mobile market’s scalability and performance requirements. Because UFS is a serial and scalable interface, it is targeted to replace eMMC for embedded flash interfaces in new and emerging designs.

UFS offers scalability from 1.25 to 5.8 Gbits/s per lane while maintaining low power consumption due to a low energy-per-bit ratio. Furthermore, it significantly increases random read/write performance. In contrast to eMMC, UFS provides full duplex communication. Its serial interface saves space in the final UFS device designs due to a smaller number of required pins. In addition to the well-established features offered by eMMC, UFS supports command queuing to harness the power of multi-tasking operating systems and multi-core CPUs. And, UFS builds on the well-established SCSI Architecture Model, which allows reuse of existing SCSI software stacks.

Development Of The Standards

Synopsys and Toshiba have been contributing members of the standards bodies behind UFS (JEDEC) and UniPro and M-PHY (MIPI Alliance) for several years to help guide the evolution of the protocols. The specification for UniPro is extremely complex, and to implement UniPro well, it is essential to understand the application space as well as the function of the protocol.

By using third-party intellectual property (IP) that supports all UniPro-based protocols, design teams can reduce integration risk and meet their time-to-market requirements. Ideally, UniPro controller IP should be developed with potential high-end consumer and mobile applications in mind and be highly configurable to support different applications on the host or on the device side, including mobile storage devices using UFS, image sensors using CSI-3, and future display ICs using DSI-2.

Being able to service all of the UniPro-based protocols helps design teams reduce integration risk and meet their time-to-market requirements. The UniPro controller can be used as a platform to implement the application layer (e.g., a CSI-3 device for image sensor ICs) to maintain the product’s differentiation.

M-PHY Foundation

Both UniPro and UFS implementations are used on the MIPI M-PHY, which supports data rates between 1.25 and 5.8 Gbits/s and up to four receive and four transmit lanes. Other features include power-efficient clock generation for high-speed and low-speed clocks and built-in diagnostics and automated test equipment (ATE) functionality for improved testing. Third-party IP should be compatible with M-PHY Type I M-PORT, supporting the standard Reference M-PHY Module Interface(RMMI) to the protocol layer, which is the de-facto standard interface for LLI, SSIC, M-PCIe, and UniPro.

The industry expects future enhancements in mobile interfaces to demand even higher speeds. To meet these demands, an M-PHY should support the High Speed Gear3 rate of up to 5.8 Gbits/s. By investing in IP that can support protocol enhancements and extensions to higher speeds, instead of adding lanes, design teams can future-proof their designs.

UniPro Controller Features

The MIPI UniPro controller includes a physical-layer (PHY) adaptation layer, a data link layer, a network layer, and a transport layer (Fig. 1). It incorporates an easy-to-use interface to the application layer including read and write interfaces via C-ports and a configuration interface to the device management entity (DME). It connects to the M-PHY via the standard RMMI.

1. The UniPro controller architecture takes a layered approach.

To meet the needs of a specific mobile application, such as a storage IC device that requires one or two Rx lanes and one or two Tx lanes, design teams should look for a UniPro controller that can be configured through the following parameters:

• Number of C-ports (1 to 2048) and data width (16, 32, 64, or 128 bits)

• Number of Rx and Tx lanes to M-PHY (range 1 to 4)

• Tx and Rx buffer depths

• All traffic classes

• Number of L4 test features

• Device Descriptor Block (DDB) settings

The UniPro controller handles the dataflow and the datastream going back and forth from the media (M-PHY) to the application layer to simplify the application implementation. It also manages the complexity in the protocol itself while maintaining reliability through an intelligent application-specific implementation.

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UFS Host Controller Features

The UFS host controller that runs on top of the M-PHY incorporates both the UniPro controller and the UFS host application layer. It also has multiple interfaces to the system-on-chip (SoC) and incorporates a pre-instantiated UniPro controller that is optimized for a UFS host application. Furthermore, the UFS host controller manages the protocol between the host and the storage device, sending all the commands and managing storage both in and out (Fig. 2).

2. The UFS host controller architecture is based on the M-PHY.

Figure 3 shows a typical system configuration. The box at the top of the diagram represents the host processor, and the bottom box is the storage IC. Design teams for UFS storage devices can differentiate their designs by creating their own UFS device controllers while using off-the-shelf UniPro and M-PHY IP.

3. A typical system configuration employs a UFS host and UniPro controller.

 

Future-Proof M-PHY

The M-PHY specification supports a variety of applications by implanting different circuitry to support Type-I and Type-II applications. Providing an application-optimized M-PHY Type-I solution that supports UFS allows customers to reduce the area used to implement the high-performance interfaces based on this M-PHY. The RMMI used with the M-PHY interoperates with standard protocols such as UniPro, UFS, CSI-3, USB 3.0 SSIC, M-PCIe, LLI, and DigRFv4 (Fig. 4).

4. M-PHY supports all protocols.

Designers should look for third-party IP that offers the Gear3 M-PHY in a variety of process nodes, which allows them to future-proof their designs to existing and evolving standards. New and evolving standards require higher performance, and high-quality IP allows designers to utilize the same number of lanes while reducing power consumption in operation and standby modes.

FPGA Prototyping

To shorten time-to-market and reduce risk, design teams can opt to validate that their SoCs work with other devices by taking advantage of hardware prototypes. With an FPGA-based prototyping system that incorporates a UniPro controller or UFS host controller, designers can easily test interoperability between system components (Fig. 5 and Fig. 6). When selecting a prototyping solution, look for proven UniPro and UFS platforms that can be used for UFS, CSI-3 implementation, or future protocols such as DSI-2.

5. The UniPro controller prototyping system supports up to four Rx and four Tx lanes.

6. The UFS host controller prototyping system supports the JEDEC UFS v1.1 standard.

UFS Host-To-Device Interoperability

High-speed serial links such as M-PHY use a relatively complex protocol to control power state transitions and guarantee data reliability. The MIPI and JEDEC standard specifications have been designed to guarantee interoperability between multiple devices using the same standard specification. Such interoperability offers many benefits to the whole mobile ecosystem. It opens up opportunities for new products that can be easily connected to various mobile application processors and stimulate innovative solutions. However, due to the complexity of the specification, some implementations don’t fully comply with the specifications. Using proven protocol IP ensures interoperability.

Synopsys and Toshiba have developed an intricate interoperability test methodology for UFS. The methodology includes testing the underlying UniPro protocol stack, UTP layer testing, and UFS-specific features testing. The interoperability tests run on the Synopsys UFS host controller platform with UFS software drivers and a Toshiba UFS memory prototyping system. Such testing goes far beyond simple writing and reading the UFS memory. Synopsys and Toshiba successfully completed their interoperability testing in October 2012.

Collaborating For Low Risk

Creating complex IP based on industry standards requires close collaboration with industry partners. Designers should make sure their IP vendor’s collaboration efforts include:

• Working closely with foundries to ensure that the IP development aligns with foundry roadmaps and latest process nodes

• Working with test equipment manufacturers to ensure that the test equipment manufacturers’ products work with the latest implementation of the specification and to enable them to test their own implementations using the IP solutions

• Collaborating with peripheral and component vendors to ensure that the IP is compatible with the vendors’ image sensors, storage devices, displays, and radio-frequency ICs (RFICs)

Industry partners should aim to build a healthy ecosystem that enables semiconductor vendors developing SoCs used in mobile devices to remove barriers and accelerate the pace of adoption of new standards.

A Complete IP Solution

The Synopsys IP portfolio addresses many of the requirements of today’s application processors. As well as providing PHYs and controllers, the company’s IP solutions include verification IP, sample software that gives developers a head start in building drivers, and boards that enable design teams to prototype their hardware in parallel to the ASIC. Figure 7 shows Synopsys’ M-PHY operating at Gear1, Gear2, and Gear3. The High-Speed Gear3 operation of the Synopsys DesignWare M-PHY was demonstrated at the March 2013 MIPI Face-to-Face event. This was the industry’s first silicon-proven HS-Gear3 M-PHY to be shown publicly.

7. Synopsys’ first-generation silicon M-PHY delivers a clean eye diagram.

The UniPro controller offers application-optimized implementation for all host and device storage (UFS), camera (CSI-3), and display (DSI-2) applications. Both the UniPro v1.41 and UFS v1.1 controller IP are available now.

As the industry continues to push for higher performance, the JEDEC UFS standard will continue to evolve and expect to utilize HS-Gear3 and multi-lane capabilities. Having M-PHY and UniPro capable of supporting HS-Gear3 and multi-lane helps adoption of upcoming JEDEC UFS standard that is in development.

Summary

The use of pre-designed, configurable IP, including M-PHY IP, enables design teams to create high-performance chip-to-chip interfaces between host processors and device ICs while reducing risk. Synopsys offers a complete UFS host solution and makes a UniPro-based platform available for vendors to develop the application layer. By maintaining in-house control of the application layer of the device IC interfaces (e.g., storage or image sensor), design teams can ensure that they differentiate and add value to their overall solutions. By continuing to collaborate with partners such as Toshiba, Synopsys is working to build a healthy and robust ecosystem for faster JEDEC UFS adoption.

Ariel Lasry serves as chief engineer in Toshiba Electronics Europe’s strategic business planning department. He also serves as the Toshiba Corporation representative to the MIPI Alliance Board of Directors. He brings more than 19 years of experience in the semiconductor industry covering various functions such as business development, technical product marketing, standardization, SoC design architecture, and LSI design. Prior to joining Toshiba, he served as senior microprocessor design engineer at SGS-Thomson Microelectronics (today STMicroelectronics). He graduated from Ecole Supérieur d’Electricité (SUPELEC) in Paris.

Hezi Saar serves as a staff product marketing manager at Synopsys and is responsible for its DesignWare MIPI controller and PHY IP product line. He brings more than 16 years of experience in the semiconductor and electronics industries in embedded systems. Prior to joining Synopsys, he was responsible for advanced interface IP at Virage Logic, before it was acquired by Synopsys, and had also served as senior product marketing manager leading Actel’s Flash FPGA product lines. He holds a BS from Tel Aviv University in computer science and economics and an MBA from Columbia Southern University.

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